From patchwork Fri Dec 18 07:21:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: shengjiangwu X-Patchwork-Id: 558780 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CD5D81402F0 for ; Fri, 18 Dec 2015 20:01:44 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ADE7CA75C7; Fri, 18 Dec 2015 10:01:40 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id N1zAjj6hy8hG; Fri, 18 Dec 2015 10:01:40 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BF9A9A75AF; Fri, 18 Dec 2015 10:01:39 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9F3054BCB9 for ; Fri, 18 Dec 2015 08:20:22 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OjKyjJx-DrBJ for ; Fri, 18 Dec 2015 08:20:22 +0100 (CET) X-Greylist: delayed 501 seconds by postgrey-1.34 at theia; Fri, 18 Dec 2015 08:20:18 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mr11p00im-asmtp004.me.com (mr11p00im-asmtp004.me.com [17.110.69.135]) by theia.denx.de (Postfix) with ESMTPS id 3E3774BCA7 for ; Fri, 18 Dec 2015 08:20:18 +0100 (CET) Received: from localhost (unknown [119.6.15.114]) by mr11p00im-asmtp004.me.com (Oracle Communications Messaging Server 7.0.5.36.0 64bit (built Sep 8 2015)) with ESMTPSA id <0NZJ00FW0LPPV910@mr11p00im-asmtp004.me.com> for u-boot@lists.denx.de; Fri, 18 Dec 2015 07:20:16 +0000 (GMT) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2015-12-18_03:,, signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 clxscore=1015 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1510270003 definitions=main-1512180138 From: shengjiangwu To: u-boot@lists.denx.de Date: Fri, 18 Dec 2015 15:21:41 +0800 Message-id: <1450423301-24778-1-git-send-email-shengjiangwu@icloud.com> X-Mailer: git-send-email 1.7.9.5 X-Mailman-Approved-At: Fri, 18 Dec 2015 10:01:37 +0100 Cc: Marek Vasut , shengjiangwu , Pavel Machek , Chin Liang See , Stefan Roese Subject: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock. Signed-off-by: shengjiangwu Cc: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese --- board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------ board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 442b1e0..06783dc 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = { 2, /* MIXED1IO12 */ 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ 0, /* MIXED1IO21 */ 0, /* MIXED2IO0 */ 0, /* MIXED2IO1 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 42905f4..eccc705 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -14,7 +14,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 @@ -32,7 +32,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511