From patchwork Mon Dec 14 17:03:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 556563 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 8919B1402C9 for ; Tue, 15 Dec 2015 04:05:01 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 06FEB4BABC; Mon, 14 Dec 2015 18:04:55 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xhB0P-7JrMWx; Mon, 14 Dec 2015 18:04:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 920634BAAC; Mon, 14 Dec 2015 18:04:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8CA1F4BA9A for ; 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Mon, 14 Dec 2015 09:04:35 -0800 (PST) Received: from localhost.localdomain ([123.236.183.119]) by smtp.gmail.com with ESMTPSA id q70sm43634096pfa.12.2015.12.14.09.04.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Dec 2015 09:04:34 -0800 (PST) From: Jagan Teki To: u-boot@lists.denx.de Date: Mon, 14 Dec 2015 22:33:54 +0530 Message-Id: <1450112634-6538-3-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1450112634-6538-1-git-send-email-jteki@openedev.com> References: <1450112634-6538-1-git-send-email-jteki@openedev.com> Cc: Jagan Teki , Fabio Estevam Subject: [U-Boot] [PATCH 3/3] sf: Fix quad bit set for micron devices X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Setting up quad bit for micron devices need to do the same way as other flash devices like spansion, winbond etc does using enhanced volatile config register so this patch adds this support instead of printing "QEB is volatile" Cc: Bin Meng Cc: Peter Pan Cc: Fabio Estevam Signed-off-by: Jagan Teki --- drivers/mtd/spi/sf_internal.h | 3 ++ drivers/mtd/spi/spi_flash.c | 66 +++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 67 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 561abc3..55ba81e 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -77,6 +77,7 @@ enum spi_nor_option_flags { #define CMD_WRITE_DISABLE 0x04 #define CMD_WRITE_ENABLE 0x06 #define CMD_QUAD_PAGE_PROGRAM 0x32 +#define CMD_WRITE_EVCR 0x61 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -90,6 +91,7 @@ enum spi_nor_option_flags { #define CMD_READ_STATUS1 0x35 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#define CMD_READ_EVCR 0x65 /* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR @@ -104,6 +106,7 @@ enum spi_nor_option_flags { #define STATUS_QEB_WINSPAN BIT(1) #define STATUS_QEB_MXIC BIT(6) #define STATUS_PEC BIT(7) +#define STATUS_QEB_MICRON BIT(7) #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 6fe8c9d..2ec465a 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -73,6 +73,37 @@ static int write_sr(struct spi_flash *flash, u8 ws) return 0; } +#ifdef CONFIG_SPI_FLASH_STMICRO +static int read_evcr(struct spi_flash *flash, u8 *evcr) +{ + int ret; + const u8 cmd = CMD_READ_EVCR; + + ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1); + if (ret < 0) { + debug("SF: error reading EVCR\n"); + return ret; + } + + return 0; +} + +static int write_evcr(struct spi_flash *flash, u8 evcr) +{ + u8 cmd; + int ret; + + cmd = CMD_WRITE_EVCR; + ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1); + if (ret < 0) { + debug("SF: error while writing EVCR register\n"); + return ret; + } + + return 0; +} +#endif + #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) static int read_cr(struct spi_flash *flash, u8 *rc) { @@ -843,6 +874,38 @@ static int spansion_quad_enable(struct spi_flash *flash) } #endif +#ifdef CONFIG_SPI_FLASH_STMICRO +static int micron_quad_enable(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = read_evcr(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_MICRON) { + ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON); + if (ret < 0) + return ret; + } else { + debug("SF: Micron EVCR Quad bit clear\n"); + } + + /* read EVCR and check it */ + ret = read_evcr(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_MICRON) { + printf("SF: Micron EVCR Quad bit not clear\n"); + return -EINVAL; + } + + return ret; +} +#endif + static int set_quad_mode(struct spi_flash *flash, u8 idcode0) { switch (idcode0) { @@ -857,8 +920,7 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0) #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - debug("SF: QEB is volatile for %02x flash\n", idcode0); - return 0; + return micron_quad_enable(flash); #endif default: printf("SF: Need set QEB func for %02x flash\n", idcode0);