From patchwork Mon Dec 14 11:58:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 556410 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 00F1F1402D2 for ; Mon, 14 Dec 2015 23:00:15 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E9704BA0E; Mon, 14 Dec 2015 12:59:36 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BYXVqLfoGRey; Mon, 14 Dec 2015 12:59:36 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D4D824BA4C; Mon, 14 Dec 2015 12:59:15 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ECDD04B884 for ; Mon, 14 Dec 2015 12:58:58 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Z15wHeb9PQhL for ; Mon, 14 Dec 2015 12:58:58 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mo4-p05-ob.smtp.rzone.de (mo4-p05-ob.smtp.rzone.de [81.169.146.183]) by theia.denx.de (Postfix) with ESMTPS id A0D614B61D for ; Mon, 14 Dec 2015 12:58:50 +0100 (CET) X-RZG-AUTH: :IW0NeWC7b/q2i6W/qstXb1SBUuFnrGohfvxEndrDXKjzPMsB3oimjD61I4fPQhgcz213 X-RZG-CLASS-ID: mo05 Received: from stefan-work.domain_not_set.invalid (b9168f50.cgn.dg-w.de [185.22.143.80]) by post.strato.de (RZmta 37.14 AUTH) with ESMTPA id z0565arBEBwoAVK; Mon, 14 Dec 2015 12:58:50 +0100 (CET) From: Stefan Roese To: u-boot@lists.denx.de Date: Mon, 14 Dec 2015 12:58:43 +0100 Message-Id: <1450094329-11674-8-git-send-email-sr@denx.de> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1450094329-11674-1-git-send-email-sr@denx.de> References: <1450094329-11674-1-git-send-email-sr@denx.de> Cc: Luka Perkov Subject: [U-Boot] [PATCH 08/14] arm: mvebu: Don't disable cache at startup on Armada XP at all X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch leaces the cache configuration untouched for the AXP in the setup done by the BootROM. Resulting in the cache still being enabled at the startup of U-Boot. This leads to a slightly faster boot to the U-Boot prompt (or Linux of course). Signed-off-by: Stefan Roese Cc: Luka Perkov --- arch/arm/mach-mvebu/cpu.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 071b13b..6c11609 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -246,13 +246,15 @@ int arch_cpu_init(void) * in the macros / defines in the U-Boot header (soc.h). */ - /* - * To fully release / unlock this area from cache, we need - * to flush all caches and disable the L2 cache. - */ - icache_disable(); - dcache_disable(); - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + if (mvebu_soc_family() == MVEBU_SOC_A38X) { + /* + * To fully release / unlock this area from cache, we need + * to flush all caches and disable the L2 cache. + */ + icache_disable(); + dcache_disable(); + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + } /* * We need to call mvebu_mbus_probe() before calling @@ -399,14 +401,13 @@ void enable_caches(void) void v7_outer_cache_enable(void) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - - /* The L2 cache is already disabled at this point */ - if (mvebu_soc_family() == MVEBU_SOC_AXP) { + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; u32 u; + /* The L2 cache is already disabled at this point */ + /* * For Aurora cache in no outer mode, enable via the CP15 * coprocessor broadcasting of cache commands to L2.