From patchwork Tue Dec 8 14:44:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nathan Rossi X-Patchwork-Id: 553928 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 662831402C4 for ; Wed, 9 Dec 2015 01:45:09 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nathanrossi-com.20150623.gappssmtp.com header.i=@nathanrossi-com.20150623.gappssmtp.com header.b=TtRB/4bd; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 47C324B85E; Tue, 8 Dec 2015 15:45:07 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4Ek897CD3ya6; Tue, 8 Dec 2015 15:45:07 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C22F34B850; Tue, 8 Dec 2015 15:45:06 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AE7EE4B84F for ; Tue, 8 Dec 2015 15:45:02 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jPYv0tJqZvzs for ; Tue, 8 Dec 2015 15:45:02 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f46.google.com (mail-pa0-f46.google.com [209.85.220.46]) by theia.denx.de (Postfix) with ESMTPS id 393B94B84E for ; Tue, 8 Dec 2015 15:44:58 +0100 (CET) Received: by pacwq6 with SMTP id wq6so13007028pac.1 for ; Tue, 08 Dec 2015 06:44:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nathanrossi-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=Ry1zM2PQ6TxjnWuDGGsao31ZBrK1q1Q1oNFvFPMAwM0=; b=TtRB/4bdMx2R7Rm7kC00azkv7v4cazFGvGKuV9W8WoORLl4I6sT7LYUHLoystkNUse U+daApl2fi4l2m7/Wl44Jx5YXackxaX6nmF46gULE95IkIjOVE9TCr6ggLLsvMbw0Bhu 6dpVMGEOFjffKyHQQEPMPSzGgE5Winig+IbRneG587zya2IfaoU2am/yJVVgpsfujAEr kyKTm2CA8YGeKeKsqiKXA7GlmknXk+GiwKmrLn4iuBja44rx6KvAExACNhTxz/FA4egB AuGgBTjnaCJRnUBx4/7M34zbHF5wyd9dpWEv61Zyr+8FOifnvKymFpxs4zU5IXEiBcdx G2kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Ry1zM2PQ6TxjnWuDGGsao31ZBrK1q1Q1oNFvFPMAwM0=; b=Oxx9bB15ayTuV/btbURz6TV8vZ0lUqthZghT5j5nKI7bEqZDNWY3rBnJMsEX+W9v2W h6C9MiwIff3FBmfKmv8+7ZfmHWvMTGXyW32wmGNPtCm178jYT6/YaFgt6v1LhqFUwpbD gmEaXmCPCM6Q7qyZey2NMkmExOaEi2vV28kswkbH2SZjm1E2CCpAh5l9Ya29BHWPGsKJ ZIZ+REtgrS5EuGIcNFG3MdZqQVKQOOfJR4En2QkgatNxcw32/WqhDNbiDrrY0GuEN75e 1gBD1sQH0vXmjazWffQ2fJCgSg+4C6BWvNGqUjtSSaUKFrn/LodkuZXXf8m6l0cf1pOM W0Pw== X-Gm-Message-State: ALoCoQkdltEfsBP9HFgoINF6ULFDWsxXWXZpy+LQmj7PaepkygkhzpVpRGM2floqvC4fmtMKCfxpFJFvdPhO0eWpsAM++A3Khg== X-Received: by 10.66.55.72 with SMTP id q8mr347848pap.136.1449585896885; Tue, 08 Dec 2015 06:44:56 -0800 (PST) Received: from nathanbox.home.gateway ([103.58.216.129]) by smtp.gmail.com with ESMTPSA id n18sm5307966pfi.29.2015.12.08.06.44.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Dec 2015 06:44:55 -0800 (PST) From: Nathan Rossi To: u-boot@lists.denx.de Date: Wed, 9 Dec 2015 00:44:40 +1000 Message-Id: <1449585883-13332-1-git-send-email-nathan@nathanrossi.com> X-Mailer: git-send-email 2.6.2 Cc: Jagan Teki , Siva Durga Prasad Paladugu , Nathan Rossi Subject: [U-Boot] [PATCH] spi: zynq_qspi: Add configuration to disable LQSPI feature X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When the Zynq Boot ROM code loads the payload from QSPI it uses the LQSPI feature of the QSPI device, however it does not clean up its configuration before handing over to the payload which leaves the device confgured to by-pass the standard non-linear operating mode. This ensures the Linear QSPI mode is disabled before re-enabling the device. Signed-off-by: Nathan Rossi Cc: Jagan Teki Cc: Siva Durga Prasad Paladugu Cc: Simon Glass --- drivers/spi/zynq_qspi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 5825c6d..b98663c 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ +#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */ /* zynq qspi Transmit Data Register */ #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */ @@ -68,6 +69,9 @@ struct zynq_qspi_regs { u32 txd1r; /* 0x80 */ u32 txd2r; /* 0x84 */ u32 txd3r; /* 0x88 */ + u32 reserved1[5]; + u32 lqspicfg; /* 0xA0 */ + u32 lqspists; /* 0xA4 */ }; /* zynq qspi platform data */ @@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) ZYNQ_QSPI_CR_MSTREN_MASK; writel(confr, ®s->cr); + /* Disable the LQSPI feature */ + confr = readl(®s->lqspicfg); + confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK; + writel(confr, ®s->lqspicfg); + /* Enable SPI */ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); }