From patchwork Tue Dec 8 03:38:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 553731 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C0FE914029C for ; Tue, 8 Dec 2015 14:51:30 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=RFQxV4ku; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 43CBEA746E; Tue, 8 Dec 2015 04:50:46 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bYMEOXRcXjbu; Tue, 8 Dec 2015 04:50:46 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BF6C5A7470; Tue, 8 Dec 2015 04:49:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8B6F34B704 for ; Tue, 8 Dec 2015 04:49:22 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SaZjtHx47FE4 for ; Tue, 8 Dec 2015 04:49:22 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-oi0-f52.google.com (mail-oi0-f52.google.com [209.85.218.52]) by theia.denx.de (Postfix) with ESMTPS id 16D994B6F9 for ; Tue, 8 Dec 2015 04:49:19 +0100 (CET) Received: by oixx65 with SMTP id x65so4008869oix.0 for ; Mon, 07 Dec 2015 19:49:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=kqIA2eUnmgX2PpkjiDtWkBTQKkSmG3spQ68am5Om6pY=; b=RFQxV4kutlqLHRznwXbsUk2r5VmqoZixkwtEzXYUGm610QSnUUDyyhiFqGuWRjtdY8 wWAJ5ZQ+E23dy5GFg1k2hmADDgXsDCH0udbAwdnH00yDInsdxlHUCjlYHsvcA3vjlk21 xmwGPhN+Ogw0ou224a/SODclH8qTWmCNFkhPx9RUbUc99gNouES/XjiX3jB/B6xtMIns ZsTdcxXq0R8UFq1youbVsUE1AwcPfTHvVbDxUTsqawEVIJw0meR+Q9PL2kRiB7qRoM3W Hnw7xQ2El8BJr0VaQAWbL97XrWt1CVUJeSM77Xz51T+JDEAeLuiOT82uLEykEcSpSRZM kvVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=kqIA2eUnmgX2PpkjiDtWkBTQKkSmG3spQ68am5Om6pY=; b=MP9IFjluqIGmviCAHgc3sWIQNehHfb4p3LTcUMVzdery8euIoutuuaZUW9x+3/cQWO nbeF0PYjEPeSRa43Y2siZz/BZTyzOYvZR10/PQqocE2ulSnh8/EcufcHplSE+g5kyGc9 XBGHVqComPn5I7vkD4aZP6boPXsZO03xLnfU9U8Mzz2DzhbTZXBwS35w4bqnQgR8p2eM wNSS2zUJzd/BT6FMsS0fknv2lNsnWncnslp34rWEz8/jFuol//XKvteSxD8OMZECQ6hG y4UffxYvgg0BQXcb6JKzrU7hQQqx/pvTDUn8xHR2M0UtgEYMxxFLfKFJZUiqg+RuPsU6 IzBw== X-Gm-Message-State: ALoCoQlTYU7LD1SXsKdFjzNCgoDDI7ZjL1jRN0zd+QSI7DlQj5D6DswDagA43HYwMQyb2o0L5Fa/S+vtHtsY8ju3zmpjp/caxg== X-Received: by 10.202.176.66 with SMTP id z63mr892106oie.61.1449546557848; Mon, 07 Dec 2015 19:49:17 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by smtp.gmail.com with ESMTPSA id iq6sm609344obb.0.2015.12.07.19.49.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 07 Dec 2015 19:49:15 -0800 (PST) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id AD6F4221D18; Mon, 7 Dec 2015 20:39:21 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Mon, 7 Dec 2015 20:38:46 -0700 Message-Id: <1449545956-2772-28-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.6.0.rc2.230.g3dd15c0 In-Reply-To: <1449545956-2772-1-git-send-email-sjg@chromium.org> References: <1449545956-2772-1-git-send-email-sjg@chromium.org> Cc: Graeme Russ Subject: [U-Boot] [PATCH 27/57] x86: ivybridge: Move northbridge and PCH init into drivers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/bd82x6x.c | 42 -------------------- arch/x86/cpu/ivybridge/northbridge.c | 55 +++++++++++++++++++++++++-- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - board/google/chromebook_link/link.c | 8 ---- 4 files changed, 52 insertions(+), 54 deletions(-) diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index cf30a3a..799d5cb 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -17,45 +17,6 @@ #include #include -void bd82x6x_pci_init(pci_dev_t dev) -{ - u16 reg16; - u8 reg8; - - debug("bd82x6x PCI init.\n"); - /* Enable Bus Master */ - reg16 = x86_pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER; - x86_pci_write_config16(dev, PCI_COMMAND, reg16); - - /* This device has no interrupt */ - x86_pci_write_config8(dev, INTR, 0xff); - - /* disable parity error response and SERR */ - reg16 = x86_pci_read_config16(dev, BCTRL); - reg16 &= ~(1 << 0); - reg16 &= ~(1 << 1); - x86_pci_write_config16(dev, BCTRL, reg16); - - /* Master Latency Count must be set to 0x04! */ - reg8 = x86_pci_read_config8(dev, SMLT); - reg8 &= 0x07; - reg8 |= (0x04 << 3); - x86_pci_write_config8(dev, SMLT, reg8); - - /* Will this improve throughput of bus masters? */ - x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06); - - /* Clear errors in status registers */ - reg16 = x86_pci_read_config16(dev, PSTS); - /* reg16 |= 0xf900; */ - x86_pci_write_config16(dev, PSTS, reg16); - - reg16 = x86_pci_read_config16(dev, SECSTS); - /* reg16 |= 0xf900; */ - x86_pci_write_config16(dev, SECSTS, reg16); -} - static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; @@ -106,10 +67,7 @@ int bd82x6x_init_extra(void) return -EINVAL; } - bd82x6x_pci_init(PCH_DEV); bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); - northbridge_enable(PCH_DEV); - northbridge_init(PCH_DEV); return 0; } diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 48c8cd7..2e63552 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -21,6 +21,45 @@ static int bridge_revision_id = -1; +static void bd82x6x_pci_init(pci_dev_t dev) +{ + u16 reg16; + u8 reg8; + + debug("bd82x6x PCI init.\n"); + /* Enable Bus Master */ + reg16 = x86_pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER; + x86_pci_write_config16(dev, PCI_COMMAND, reg16); + + /* This device has no interrupt */ + x86_pci_write_config8(dev, INTR, 0xff); + + /* disable parity error response and SERR */ + reg16 = x86_pci_read_config16(dev, BCTRL); + reg16 &= ~(1 << 0); + reg16 &= ~(1 << 1); + x86_pci_write_config16(dev, BCTRL, reg16); + + /* Master Latency Count must be set to 0x04! */ + reg8 = x86_pci_read_config8(dev, SMLT); + reg8 &= 0x07; + reg8 |= (0x04 << 3); + x86_pci_write_config8(dev, SMLT, reg8); + + /* Will this improve throughput of bus masters? */ + x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06); + + /* Clear errors in status registers */ + reg16 = x86_pci_read_config16(dev, PSTS); + /* reg16 |= 0xf900; */ + x86_pci_write_config16(dev, PSTS, reg16); + + reg16 = x86_pci_read_config16(dev, SECSTS); + /* reg16 |= 0xf900; */ + x86_pci_write_config16(dev, SECSTS, reg16); +} + int bridge_silicon_revision(void) { if (bridge_revision_id < 0) { @@ -213,14 +252,12 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev) dm_pci_write_config8(dev, PAM6, 0x33); } -static int bd82x6x_northbridge_probe(struct udevice *dev) +static int bd82x6x_northbridge_early_init(struct udevice *dev) { const int chipset_type = SANDYBRIDGE_MOBILE; u32 capid0_a; u8 reg8; - if (gd->flags & GD_FLG_RELOC) - return 0; /* Device ID Override Enable should be done very early */ dm_pci_read_config32(dev, 0xe4, &capid0_a); @@ -242,6 +279,18 @@ static int bd82x6x_northbridge_probe(struct udevice *dev) return 0; } +static int bd82x6x_northbridge_probe(struct udevice *dev) +{ + if (!(gd->flags & GD_FLG_RELOC)) + return bd82x6x_northbridge_early_init(dev); + + bd82x6x_pci_init(PCH_DEV); + northbridge_enable(PCH_DEV); + northbridge_init(PCH_DEV); + + return 0; +} + static const struct udevice_id bd82x6x_northbridge_ids[] = { { .compatible = "intel,bd82x6x-northbridge" }, { } diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index fc7fc6d..0f4fe47 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -9,7 +9,6 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); -void bd82x6x_pci_init(pci_dev_t dev); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node); diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 1b97a8f..d12d742 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -14,14 +14,6 @@ int arch_early_init_r(void) { - struct udevice *dev; - int ret; - - /* Make sure the platform controller hub is up and running */ - ret = uclass_get_device(UCLASS_PCH, 0, &dev); - if (ret) - return ret; - return 0; }