From patchwork Tue Dec 8 03:38:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 553767 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4EA631402C9 for ; Tue, 8 Dec 2015 15:04:41 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=Hddhb7qL; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 000244B7E3; Tue, 8 Dec 2015 05:04:34 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1tM8gP3nG5Oo; Tue, 8 Dec 2015 05:04:34 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5D90F4B7DC; Tue, 8 Dec 2015 05:04:27 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8EE334B742 for ; Tue, 8 Dec 2015 05:04:19 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ys2VPeDdPl3M for ; Tue, 8 Dec 2015 05:04:19 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f177.google.com (mail-ob0-f177.google.com [209.85.214.177]) by theia.denx.de (Postfix) with ESMTPS id 298D04B785 for ; Tue, 8 Dec 2015 05:04:14 +0100 (CET) Received: by obc18 with SMTP id 18so4194445obc.2 for ; Mon, 07 Dec 2015 20:04:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=YQP0n8F4cIXzK1Vskb/4AjEevOn3dPkXm+sngxeADdE=; b=Hddhb7qLHYITSfbgBLo1x+KzRk2QI+H45L2s24v/VfAYdR+ldxALEiE49A1SlXS00W UfBAOGt5hxamosx/XyUga5zRDG0dBYL/Y3sXUvMFEy4AK3pmu+QpHEqiq3jBpWE/FgXS 1E29R+7+2bBsG0vk0IhDBvuPtUYroV0dBgbp16GKS2t04wHnBPuT6JwfS6SXoAUC0lC9 EEnPTmSJijqhERF/1Ozpjb5+52Sh+WVuGvF25qyCjm4FDlXyAcnBaiTyYjoGf8e0OI06 htOwmmUcnMX09ZIpTlg2/jayqyio9LZQLuWRwDlJIEAF1FJVFXEATK3nIpEpgL6G/saK y7og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=YQP0n8F4cIXzK1Vskb/4AjEevOn3dPkXm+sngxeADdE=; b=Wi9XKbFeQHQcXiJvi7uAHq9ePOh8NlOb3MS5DjCwvTQZwFyQK4Sb4/C/JXnYTDGbRg 24eUqWee7ykA+V2qYLWKy9e0k/w9rib/i9ClahB+ylM7GQCKBObGg5AJhsaVb5zk5dcq y5dfaZU5rI5zZQwLZUNnkA3GfNeiibVGKmU4T+kN8L87Z1RQhIL0tnerBSP6/IZdNki2 2s0RdaMgs0Vet2uwEAbkDpAuGpxLiii7LlXi8qRawqNU4j2i7kBtM/sanDZsMy26Et7n dxtoxHsOEYXUqzfFoPQITrNIC59DWBOg2N3VpCAE8Y2s+u7THqElC/5ifNacKzozjuL9 824g== X-Gm-Message-State: ALoCoQk3PPT7PO0yarZhIq2ff4H/tMx0kygGGhHnV8sFhaDnPUzNgKVBvwq4U/invWVhGFCN7fnwLp5V9jXmMmgYEUEGxZedTw== X-Received: by 10.60.43.170 with SMTP id x10mr1000787oel.68.1449547453618; Mon, 07 Dec 2015 20:04:13 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by smtp.gmail.com with ESMTPSA id j131sm639243oib.0.2015.12.07.20.04.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 07 Dec 2015 20:04:12 -0800 (PST) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 38F55221A1D; Mon, 7 Dec 2015 20:39:21 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Mon, 7 Dec 2015 20:38:42 -0700 Message-Id: <1449545956-2772-24-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.6.0.rc2.230.g3dd15c0 In-Reply-To: <1449545956-2772-1-git-send-email-sjg@chromium.org> References: <1449545956-2772-1-git-send-email-sjg@chromium.org> Cc: Graeme Russ Subject: [U-Boot] [PATCH 23/57] x86: ivybridge: Move early init code into northbridge.c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This code is now part of the northbridge driver, so move it into the same place. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/early_init.c | 81 ------------------------------------ arch/x86/cpu/ivybridge/northbridge.c | 67 +++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 82 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/early_init.c diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 0c7efae..bdbd3fa 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,7 +7,6 @@ obj-y += bd82x6x.o obj-y += car.o obj-y += cpu.o -obj-y += early_init.o obj-y += early_me.o obj-y += gma.o obj-y += lpc.o diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c deleted file mode 100644 index 5b16abc..0000000 --- a/arch/x86/cpu/ivybridge/early_init.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * From Coreboot - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -static void sandybridge_setup_northbridge_bars(struct udevice *dev) -{ - /* Set up all hardcoded northbridge BARs */ - debug("Setting up static registers\n"); - dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); - dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); - dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); - /* 64MB - busses 0-63 */ - dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); - dm_pci_write_config32(dev, PCIEXBAR + 4, - (0LL + DEFAULT_PCIEXBAR) >> 32); - dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); - dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); - - /* Set C0000-FFFFF to access RAM on both reads and writes */ - dm_pci_write_config8(dev, PAM0, 0x30); - dm_pci_write_config8(dev, PAM1, 0x33); - dm_pci_write_config8(dev, PAM2, 0x33); - dm_pci_write_config8(dev, PAM3, 0x33); - dm_pci_write_config8(dev, PAM4, 0x33); - dm_pci_write_config8(dev, PAM5, 0x33); - dm_pci_write_config8(dev, PAM6, 0x33); -} - -static int bd82x6x_northbridge_probe(struct udevice *dev) -{ - const int chipset_type = SANDYBRIDGE_MOBILE; - u32 capid0_a; - u8 reg8; - - if (gd->flags & GD_FLG_RELOC) - return 0; - - /* Device ID Override Enable should be done very early */ - dm_pci_read_config32(dev, 0xe4, &capid0_a); - if (capid0_a & (1 << 10)) { - dm_pci_read_config8(dev, 0xf3, ®8); - reg8 &= ~7; /* Clear 2:0 */ - - if (chipset_type == SANDYBRIDGE_MOBILE) - reg8 |= 1; /* Set bit 0 */ - - dm_pci_write_config8(dev, 0xf3, reg8); - } - - sandybridge_setup_northbridge_bars(dev); - - /* Device Enable */ - dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); - - return 0; -} - -static const struct udevice_id bd82x6x_northbridge_ids[] = { - { .compatible = "intel,bd82x6x-northbridge" }, - { } -}; - -U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { - .name = "bd82x6x_northbridge", - .id = UCLASS_NORTHBRIDGE, - .of_match = bd82x6x_northbridge_ids, - .probe = bd82x6x_northbridge_probe, -}; diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index e95e60e..48c8cd7 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -186,3 +187,69 @@ void northbridge_enable(pci_dev_t dev) } #endif } + +static void sandybridge_setup_northbridge_bars(struct udevice *dev) +{ + /* Set up all hardcoded northbridge BARs */ + debug("Setting up static registers\n"); + dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); + dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); + dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + /* 64MB - busses 0-63 */ + dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); + dm_pci_write_config32(dev, PCIEXBAR + 4, + (0LL + DEFAULT_PCIEXBAR) >> 32); + dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); + dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + dm_pci_write_config8(dev, PAM0, 0x30); + dm_pci_write_config8(dev, PAM1, 0x33); + dm_pci_write_config8(dev, PAM2, 0x33); + dm_pci_write_config8(dev, PAM3, 0x33); + dm_pci_write_config8(dev, PAM4, 0x33); + dm_pci_write_config8(dev, PAM5, 0x33); + dm_pci_write_config8(dev, PAM6, 0x33); +} + +static int bd82x6x_northbridge_probe(struct udevice *dev) +{ + const int chipset_type = SANDYBRIDGE_MOBILE; + u32 capid0_a; + u8 reg8; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + /* Device ID Override Enable should be done very early */ + dm_pci_read_config32(dev, 0xe4, &capid0_a); + if (capid0_a & (1 << 10)) { + dm_pci_read_config8(dev, 0xf3, ®8); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == SANDYBRIDGE_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + dm_pci_write_config8(dev, 0xf3, reg8); + } + + sandybridge_setup_northbridge_bars(dev); + + /* Device Enable */ + dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); + + return 0; +} + +static const struct udevice_id bd82x6x_northbridge_ids[] = { + { .compatible = "intel,bd82x6x-northbridge" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { + .name = "bd82x6x_northbridge", + .id = UCLASS_NORTHBRIDGE, + .of_match = bd82x6x_northbridge_ids, + .probe = bd82x6x_northbridge_probe, +};