From patchwork Tue Nov 24 08:34:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Josh Wu X-Patchwork-Id: 547886 X-Patchwork-Delegate: andreas.biessmann@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6F0A61402CC for ; Tue, 24 Nov 2015 19:27:03 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 188AF4BD14; Tue, 24 Nov 2015 09:27:02 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id D5Q6snAd3r_T; Tue, 24 Nov 2015 09:27:01 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CF0C54BD1A; Tue, 24 Nov 2015 09:26:53 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2AE8C4BCF8 for ; Tue, 24 Nov 2015 09:26:43 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id stLyyR2a7a6j for ; Tue, 24 Nov 2015 09:26:42 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from eusmtp01.atmel.com (eusmtp01.atmel.com [212.144.249.242]) by theia.denx.de (Postfix) with ESMTPS id 0D8424BCF7 for ; Tue, 24 Nov 2015 09:26:38 +0100 (CET) Received: from apsmtp01.atmel.com (10.168.254.30) by eusmtp01.atmel.com (10.161.101.30) with Microsoft SMTP Server id 14.3.235.1; Tue, 24 Nov 2015 09:26:35 +0100 Received: from melon.corp.atmel.com (10.168.254.13) by apsmtp01.corp.atmel.com (10.168.254.30) with Microsoft SMTP Server id 14.3.235.1; Tue, 24 Nov 2015 16:27:45 +0800 From: Josh Wu To: Scott Wood , , U-Boot Mailing List Date: Tue, 24 Nov 2015 16:34:00 +0800 Message-ID: <1448354042-27066-2-git-send-email-josh.wu@atmel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1448354042-27066-1-git-send-email-josh.wu@atmel.com> References: <1448354042-27066-1-git-send-email-josh.wu@atmel.com> MIME-Version: 1.0 Cc: Bo Shen Subject: [U-Boot] [PATCH 1/2] atmel_nand_ecc: update pmecc registers according to sama5d2 chip X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" 1. add the pmecc register mapping for sama5d2. 2. add the pmecc error location register mapping for sama5d2. 3. add some new field that is different from old ip. 4. add sama5d2 pmecc ip version number. Signed-off-by: Josh Wu Reviewed-by: Andreas Bießmann --- drivers/mtd/nand/atmel_nand_ecc.h | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h index 79e3994..e13f385 100644 --- a/drivers/mtd/nand/atmel_nand_ecc.h +++ b/drivers/mtd/nand/atmel_nand_ecc.h @@ -58,14 +58,23 @@ struct pmecc_regs { /* 0x40 + sector_num * (0x40), Redundancy Registers */ struct { +#ifdef CONFIG_SAMA5D2 + u8 ecc[56]; /* PMECC Generated Redundancy Byte Per Sector */ + u32 reserved1[2]; +#else u8 ecc[44]; /* PMECC Generated Redundancy Byte Per Sector */ u32 reserved1[5]; +#endif } ecc_port[PMECC_MAX_SECTOR_NUM]; /* 0x240 + sector_num * (0x40) Remainder Registers */ struct { +#ifdef CONFIG_SAMA5D2 + u32 rem[16]; +#else u32 rem[12]; u32 reserved2[4]; +#endif } rem_port[PMECC_MAX_SECTOR_NUM]; u32 reserved3[16]; /* 0x440-0x47C Reserved */ }; @@ -76,6 +85,7 @@ struct pmecc_regs { #define PMECC_CFG_BCH_ERR8 (2 << 0) #define PMECC_CFG_BCH_ERR12 (3 << 0) #define PMECC_CFG_BCH_ERR24 (4 << 0) +#define PMECC_CFG_BCH_ERR32 (5 << 0) #define PMECC_CFG_SECTOR512 (0 << 4) #define PMECC_CFG_SECTOR1024 (1 << 4) @@ -120,19 +130,31 @@ struct pmecc_errloc_regs { u32 elimr; /* 0x0C Error Location Interrupt Mask Register */ u32 elisr; /* 0x20 Error Location Interrupt Status Register */ u32 reserved0; /* 0x24 Reserved */ +#ifdef CONFIG_SAMA5D2 + u32 sigma[33]; /* 0x28-0xA8 Error Location Sigma Registers */ + u32 el[32]; /* 0xAC-0x128 Error Location Registers */ + + /* + * 0x12C-0x1FC: + * Reserved for SAMA5D2. + */ + u32 reserved1[53]; +#else u32 sigma[25]; /* 0x28-0x88 Error Location Sigma Registers */ u32 el[24]; /* 0x8C-0xE8 Error Location Registers */ u32 reserved1[5]; /* 0xEC-0xFC Reserved */ +#endif /* - * 0x100-0x1F8: - * Reserved for AT91SAM9X5, AT91SAM9N12. - * HSMC registers for SAMA5D3, SAMA5D4. + * SAMA5 chip HSMC registers start here. But for 9X5 chip it is just + * reserved. + * + * Offset 0x00-0xF8: */ u32 reserved2[63]; /* - * 0x1FC: + * Offset 0xFC: * PMECC version for AT91SAM9X5, AT91SAM9N12. * HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version. */ @@ -148,10 +170,16 @@ struct pmecc_errloc_regs { #define PMERRLOC_DISABLE (1 << 0) /* For Error Location Interrupt Status Register */ +#ifdef CONFIG_SAMA5D2 +#define PMERRLOC_ERR_NUM_MASK (0x3f << 8) +#else #define PMERRLOC_ERR_NUM_MASK (0x1f << 8) +#endif + #define PMERRLOC_CALC_DONE (1 << 0) /* PMECC IP version */ +#define PMECC_VERSION_SAMA5D2 0x210 #define PMECC_VERSION_SAMA5D4 0x113 #define PMECC_VERSION_SAMA5D3 0x112 #define PMECC_VERSION_AT91SAM9N12 0x102