diff mbox

[U-Boot,01/10,v4] armv8: lsch3: Fix lane protocol parsing logic

Message ID 1446620162-21725-2-git-send-email-prabhakar@freescale.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

Prabhakar Kushwaha Nov. 4, 2015, 6:55 a.m. UTC 
Current implementation only consider SGMIIs for dpmac initialization.
XFI serdes protocols also uses dpmac.

Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 Changes for v2: Sending as it is
 Changes for v3: Sending as it is
 Changes for v4: Update SerDes Parsing logic

 .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c    | 25 ++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

Comments

York Sun Nov. 30, 2015, 5:01 p.m. UTC | #1 
On 11/03/2015 10:55 PM, Prabhakar Kushwaha wrote:
> Current implementation only consider SGMIIs for dpmac initialization.
> XFI serdes protocols also uses dpmac.
> 
> Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
>  Changes for v2: Sending as it is
>  Changes for v3: Sending as it is
>  Changes for v4: Update SerDes Parsing logic
> 
>  .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c    | 25 ++++++++++++++++++++--
>  1 file changed, 23 insertions(+), 2 deletions(-)

Squashed with patch "driver: net: ldpaa: Update the lane number to DPMAC
mapping". Applied to fsl-qoriq master. Thanks.

York
diff mbox

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 2ab8da6..918e889 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -18,6 +18,11 @@  static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 
+#ifdef CONFIG_FSL_MC_ENET
+int xfi_dpmac[XFI8 + 1];
+int sgmii_dpmac[SGMII16 + 1];
+#endif
+
 int is_serdes_configured(enum srds_prtcl device)
 {
 	int ret = 0;
@@ -116,9 +121,15 @@  void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 				wriop_init_dpmac(sd, 12, (int)lane_prtcl);
 				break;
 			default:
+				if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
+					wriop_init_dpmac(sd,
+							 xfi_dpmac[lane_prtcl],
+							 (int)lane_prtcl);
+
 				 if (lane_prtcl >= SGMII1 &&
-					   lane_prtcl <= SGMII16)
-					wriop_init_dpmac(sd, lane + 1,
+				     lane_prtcl <= SGMII16)
+					wriop_init_dpmac(sd, sgmii_dpmac[
+							 lane_prtcl],
 							 (int)lane_prtcl);
 				break;
 			}
@@ -129,6 +140,16 @@  void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 
 void fsl_serdes_init(void)
 {
+#ifdef CONFIG_FSL_MC_ENET
+	int i , j;
+
+	for (i = XFI1, j = 1; i <= XFI8; i++, j++)
+		xfi_dpmac[i] = j;
+
+	for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
+		sgmii_dpmac[i] = j;
+#endif
+
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes_init(FSL_SRDS_1,
 		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,