From patchwork Tue Oct 27 12:08:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Przemyslaw Marczak X-Patchwork-Id: 536595 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2BD8D1412F9 for ; Tue, 27 Oct 2015 23:11:59 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CED134B6F8; Tue, 27 Oct 2015 13:10:54 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 720BM_7HslP4; Tue, 27 Oct 2015 13:10:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 999774B74E; Tue, 27 Oct 2015 13:10:09 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F0B164B6D7 for ; Tue, 27 Oct 2015 13:09:34 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id B0H0KN6Ztqw1 for ; Tue, 27 Oct 2015 13:09:34 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) by theia.denx.de (Postfix) with ESMTPS id 291784B6A8 for ; Tue, 27 Oct 2015 13:09:27 +0100 (CET) Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NWV00117OFJ6U10@mailout1.w1.samsung.com> for u-boot@lists.denx.de; Tue, 27 Oct 2015 12:09:19 +0000 (GMT) X-AuditID: cbfec7f5-f794b6d000001495-4c-562f696f8c16 Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id FF.8C.05269.F696F265; Tue, 27 Oct 2015 12:09:19 +0000 (GMT) Received: from AMDC1186.digital.local ([106.116.147.185]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NWV008PTOFC0WA0@eusync1.samsung.com>; Tue, 27 Oct 2015 12:09:19 +0000 (GMT) From: Przemyslaw Marczak To: u-boot@lists.denx.de Date: Tue, 27 Oct 2015 13:08:01 +0100 Message-id: <1445947687-9917-9-git-send-email-p.marczak@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1445947687-9917-1-git-send-email-p.marczak@samsung.com> References: <1442838403-27777-1-git-send-email-p.marczak@samsung.com> <1445947687-9917-1-git-send-email-p.marczak@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprNLMWRmVeSWpSXmKPExsVy+t/xy7r5mfphBpuPGllsnLGe1eLNw82M Fus23mK36DjSwmix4/INFotvW7YxWkw//pbV4u3eTnYHDo/ZDRdZPP4+v87isXPWXXaPs3d2 MHr0bVnFGMAaxWWTkpqTWZZapG+XwJUxafspxoILNhVNNw+wNzBeMOxi5OSQEDCR6LjayA5h i0lcuLeerYuRi0NIYCmjxONvnawQTjOTxNZfp5hAqtgEDCT2XDrDDGKLCEhI/Oq/yghSxCyw lkni76ePjCAJYQF3ieOrt4HZLAKqEnv3fgBr5hVwkeg++pkZYp2cxMljk4E2cHBwCrhKdN4L h1jWwChx9cIfxgmMvAsYGVYxiqaWJhcUJ6XnGukVJ+YWl+al6yXn525ihATZ1x2MS49ZHWIU 4GBU4uE1qNALE2JNLCuuzD3EKMHBrCTCezFGP0yINyWxsiq1KD++qDQntfgQozQHi5I478xd 70OEBNITS1KzU1MLUotgskwcnFINjBm126Xr1FLnny9eqmpSfeZM8ZXLi2oFW9ZV9npz7FSM 2rvjTJaX7KkfZ5kC1Vpj1wdwvn4dsikvwODiTd05PE1aVqdKjS9k7rpj///h7oX5F15FeCe5 F26O/dC+6eCtSf+XSOzu5XzcsG5z2KsPM9JNS+e1MTjlcG+7s+3pfsPpDVdfGkz2uKnEUpyR aKjFXFScCAD2Hld+LgIAAA== Cc: Bartlomiej Zolnierkiewicz , Anand Moon , Przemyslaw Marczak Subject: [U-Boot] [PATCH V3 08/14] dm: adc: add Exynos54xx compatible ADC driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds driver for Exynos54xx ADC subsystem. The driver is implemented using driver model, amd provides ADC uclass's methods for ADC single channel operations: - adc_start_channel() - adc_channel_data() - adc_stop() The basic parameters of ADC conversion, are: - sample rate: 600KSPS - output the data as average of 8 time conversion ADC features: - sample rate: 600KSPS - resolution: 12-bit - channels: 10 (analog multiplexer) Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Cc: Simon Glass Reviewed-by: Simon Glass --- Changes V2: - new commit - move previous adc driver from SoC directory to drivers/adc Changes V3: - rework the driver to fit new API - remove call to sdelay() from driver's code - add active_channel to keep consistency between ADC request and result --- arch/arm/mach-exynos/include/mach/adc.h | 44 ++++++++++ drivers/adc/Kconfig | 9 ++ drivers/adc/Makefile | 1 + drivers/adc/exynos-adc.c | 145 ++++++++++++++++++++++++++++++++ 4 files changed, 199 insertions(+) create mode 100644 drivers/adc/exynos-adc.c diff --git a/arch/arm/mach-exynos/include/mach/adc.h b/arch/arm/mach-exynos/include/mach/adc.h index a0e26d7..9af51ab 100644 --- a/arch/arm/mach-exynos/include/mach/adc.h +++ b/arch/arm/mach-exynos/include/mach/adc.h @@ -9,6 +9,39 @@ #ifndef __ASM_ARM_ARCH_ADC_H_ #define __ASM_ARM_ARCH_ADC_H_ +#define ADC_V2_CON1_SOFT_RESET (0x2 << 1) +#define ADC_V2_CON1_STC_EN 0x1 + +#define ADC_V2_CON2_OSEL(x) (((x) & 0x1) << 10) +#define OSEL_2S 0x0 +#define OSEL_BINARY 0x1 +#define ADC_V2_CON2_ESEL(x) (((x) & 0x1) << 9) +#define ESEL_ADC_EVAL_TIME_40CLK 0x0 +#define ESEL_ADC_EVAL_TIME_20CLK 0x1 +#define ADC_V2_CON2_HIGHF(x) (((x) & 0x1) << 8) +#define HIGHF_CONV_RATE_30KSPS 0x0 +#define HIGHF_CONV_RATE_600KSPS 0x1 +#define ADC_V2_CON2_C_TIME(x) (((x) & 0x7) << 4) +#define ADC_V2_CON2_CHAN_SEL_MASK 0xf +#define ADC_V2_CON2_CHAN_SEL(x) ((x) & ADC_V2_CON2_CHAN_SEL_MASK) + +#define ADC_V2_GET_STATUS_FLAG(x) (((x) >> 2) & 0x1) +#define FLAG_CONV_END 0x1 + +#define ADC_V2_INT_DISABLE 0x0 +#define ADC_V2_INT_ENABLE 0x1 +#define INT_NOT_GENERATED 0x0 +#define INT_GENERATED 0x1 + +#define ADC_V2_VERSION 0x80000008 + +#define ADC_V2_MAX_CHANNEL 9 + +/* For default 8 time convertion with sample rate 600 kSPS - 15us timeout */ +#define ADC_V2_CONV_TIMEOUT_US 15 + +#define ADC_V2_DAT_MASK 0xfff + #ifndef __ASSEMBLY__ struct s5p_adc { unsigned int adccon; @@ -21,6 +54,17 @@ struct s5p_adc { unsigned int adcmux; unsigned int adcclrintpndnup; }; + +struct exynos_adc_v2 { + unsigned int con1; + unsigned int con2; + unsigned int status; + unsigned int dat; + unsigned int int_en; + unsigned int int_status; + unsigned int reserved[2]; + unsigned int version; +}; #endif #endif /* __ASM_ARM_ARCH_ADC_H_ */ diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index b6e226a..223b65e 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -10,3 +10,12 @@ config ADC - methods for get Vdd/Vss reference Voltage values with polarity - support supply's phandle with auto-enable - supply polarity setting in fdt + +config ADC_EXYNOS + bool "Enable Exynos 54xx ADC driver" + help + This enables basic driver for Exynos ADC compatible with Exynos54xx. + It provides: + - 10 analog input channels + - 12-bit resolution + - 600 KSPS of sample rate diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile index c4d9618..eb85b8b 100644 --- a/drivers/adc/Makefile +++ b/drivers/adc/Makefile @@ -6,3 +6,4 @@ # obj-$(CONFIG_ADC) += adc-uclass.o +obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o diff --git a/drivers/adc/exynos-adc.c b/drivers/adc/exynos-adc.c new file mode 100644 index 0000000..534e68d --- /dev/null +++ b/drivers/adc/exynos-adc.c @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +struct exynos_adc_priv { + int active_channel; + struct exynos_adc_v2 *regs; +}; + +int exynos_adc_channel_data(struct udevice *dev, int channel, + unsigned int *data) +{ + struct exynos_adc_priv *priv = dev_get_priv(dev); + struct exynos_adc_v2 *regs = priv->regs; + + if (channel != priv->active_channel) { + error("Requested channel is not active!"); + return -EINVAL; + } + + if (ADC_V2_GET_STATUS_FLAG(readl(®s->status)) != FLAG_CONV_END) + return -EBUSY; + + *data = readl(®s->dat) & ADC_V2_DAT_MASK; + + return 0; +} + +int exynos_adc_start_channel(struct udevice *dev, int channel) +{ + struct exynos_adc_priv *priv = dev_get_priv(dev); + struct exynos_adc_v2 *regs = priv->regs; + unsigned int cfg; + + /* Choose channel */ + cfg = readl(®s->con2); + cfg &= ~ADC_V2_CON2_CHAN_SEL_MASK; + cfg |= ADC_V2_CON2_CHAN_SEL(channel); + writel(cfg, ®s->con2); + + /* Start conversion */ + cfg = readl(®s->con1); + writel(cfg | ADC_V2_CON1_STC_EN, ®s->con1); + + priv->active_channel = channel; + + return 0; +} + +int exynos_adc_stop(struct udevice *dev) +{ + struct exynos_adc_priv *priv = dev_get_priv(dev); + struct exynos_adc_v2 *regs = priv->regs; + unsigned int cfg; + + /* Stop conversion */ + cfg = readl(®s->con1); + cfg |= ~ADC_V2_CON1_STC_EN; + + writel(cfg, ®s->con1); + + priv->active_channel = -1; + + return 0; +} + +int exynos_adc_probe(struct udevice *dev) +{ + struct exynos_adc_priv *priv = dev_get_priv(dev); + struct exynos_adc_v2 *regs = priv->regs; + unsigned int cfg; + + /* Check HW version */ + if (readl(®s->version) != ADC_V2_VERSION) { + error("This driver supports only ADC v2!"); + return -ENXIO; + } + + /* ADC Reset */ + writel(ADC_V2_CON1_SOFT_RESET, ®s->con1); + + /* Disable INT - will read status only */ + writel(0x0, ®s->int_en); + + /* CON2 - set conversion parameters */ + cfg = ADC_V2_CON2_C_TIME(3); /* Conversion times: (1 << 3) = 8 */ + cfg |= ADC_V2_CON2_OSEL(OSEL_BINARY); + cfg |= ADC_V2_CON2_ESEL(ESEL_ADC_EVAL_TIME_20CLK); + cfg |= ADC_V2_CON2_HIGHF(HIGHF_CONV_RATE_600KSPS); + writel(cfg, ®s->con2); + + priv->active_channel = -1; + + return 0; +} + +int exynos_adc_ofdata_to_platdata(struct udevice *dev) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + struct exynos_adc_priv *priv = dev_get_priv(dev); + + priv->regs = (struct exynos_adc_v2 *)dev_get_addr(dev); + if (priv->regs == (struct exynos_adc_v2 *)FDT_ADDR_T_NONE) { + error("Dev: %s - can't get address!", dev->name); + return -ENODATA; + } + + uc_pdata->data_mask = ADC_V2_DAT_MASK; + uc_pdata->data_format = ADC_DATA_FORMAT_BIN; + uc_pdata->data_timeout_us = ADC_V2_CONV_TIMEOUT_US; + + /* Mask available channel bits: [0:9] */ + uc_pdata->channel_mask = (2 << ADC_V2_MAX_CHANNEL) - 1; + + return 0; +} + +static const struct adc_ops exynos_adc_ops = { + .start_channel = exynos_adc_start_channel, + .channel_data = exynos_adc_channel_data, + .stop = exynos_adc_stop, +}; + +static const struct udevice_id exynos_adc_ids[] = { + { .compatible = "samsung,exynos-adc-v2" }, + { } +}; + +U_BOOT_DRIVER(exynos_adc) = { + .name = "exynos-adc", + .id = UCLASS_ADC, + .of_match = exynos_adc_ids, + .ops = &exynos_adc_ops, + .probe = exynos_adc_probe, + .ofdata_to_platdata = exynos_adc_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct exynos_adc_priv), +};