From patchwork Sat Oct 24 03:38:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 535349 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7D30714131F for ; Sat, 24 Oct 2015 14:41:14 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BB9044B693; Sat, 24 Oct 2015 05:40:40 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6zazvCg29_Q8; Sat, 24 Oct 2015 05:40:40 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 29A144B622; Sat, 24 Oct 2015 05:40:29 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9FF654B6BE for ; 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Fri, 23 Oct 2015 20:40:00 -0700 (PDT) Received: from localhost.localdomain ([1.39.13.114]) by smtp.gmail.com with ESMTPSA id tk4sm21622200pab.45.2015.10.23.20.39.57 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 Oct 2015 20:39:59 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Sat, 24 Oct 2015 09:08:55 +0530 Message-Id: <1445657950-7117-9-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445657950-7117-1-git-send-email-jteki@openedev.com> References: <1445657950-7117-1-git-send-email-jteki@openedev.com> Cc: Jagan Teki , York Sun , Haikun Wang Subject: [U-Boot] [PATCH v5 08/23] spi: fsl: Use BIT macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Replace numerical bit shift with BIT macro in fsl_*spi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: York Sun Cc: Haikun Wang Reviewed-by: Tom Rini Signed-off-by: Jagan Teki --- drivers/spi/fsl_dspi.c | 2 +- drivers/spi/fsl_espi.c | 20 ++++++++++---------- drivers/spi/fsl_qspi.c | 4 ++-- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 887edd8..c8dcb27 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; /* fsl_dspi_platdata flags */ -#define DSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0) +#define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) /* idle data value */ #define DSPI_IDLE_VAL 0x0 diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 375dc07..b1586d1 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -32,26 +32,26 @@ struct fsl_spi_slave { #define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32 -#define ESPI_EV_RNE (1 << 9) -#define ESPI_EV_TNF (1 << 8) -#define ESPI_EV_DON (1 << 14) -#define ESPI_EV_TXE (1 << 15) +#define ESPI_EV_RNE BIT(9) +#define ESPI_EV_TNF BIT(8) +#define ESPI_EV_DON BIT(14) +#define ESPI_EV_TXE BIT(15) #define ESPI_EV_RFCNT_SHIFT 24 #define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT) -#define ESPI_MODE_EN (1 << 31) /* Enable interface */ +#define ESPI_MODE_EN BIT(31) /* Enable interface */ #define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ #define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ #define ESPI_COM_CS(x) ((x) << 30) #define ESPI_COM_TRANLEN(x) ((x) << 0) -#define ESPI_CSMODE_CI_INACTIVEHIGH (1 << 31) -#define ESPI_CSMODE_CP_BEGIN_EDGCLK (1 << 30) -#define ESPI_CSMODE_REV_MSB_FIRST (1 << 29) -#define ESPI_CSMODE_DIV16 (1 << 28) +#define ESPI_CSMODE_CI_INACTIVEHIGH BIT(31) +#define ESPI_CSMODE_CP_BEGIN_EDGCLK BIT(30) +#define ESPI_CSMODE_REV_MSB_FIRST BIT(29) +#define ESPI_CSMODE_DIV16 BIT(28) #define ESPI_CSMODE_PM(x) ((x) << 24) -#define ESPI_CSMODE_POL_ASSERTED_LOW (1 << 20) +#define ESPI_CSMODE_POL_ASSERTED_LOW BIT(20) #define ESPI_CSMODE_LEN(x) ((x) << 16) #define ESPI_CSMODE_CSBEF(x) ((x) << 12) #define ESPI_CSMODE_CSAFT(x) ((x) << 8) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 868df5f..e1a0ec9 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ /* fsl_qspi_platdata flags */ -#define QSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0) +#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) /* default SCK frequency, unit: HZ */ #define FSL_QSPI_DEFAULT_SCK_FREQ 50000000 @@ -383,7 +383,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) /* Enable the module again (enable the DDR too) */ reg |= QSPI_MCR_DDR_EN_MASK; /* Enable bit 29 for imx6sx */ - reg |= (1 << 29); + reg |= BIT(29); qspi_write32(priv->flags, ®s->mcr, reg); }