From patchwork Sat Oct 24 03:38:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 535343 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D419E141316 for ; Sat, 24 Oct 2015 14:39:59 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A3F604B691; Sat, 24 Oct 2015 05:39:54 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id M4u4vAuMxD2i; Sat, 24 Oct 2015 05:39:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 953B84B693; Sat, 24 Oct 2015 05:39:53 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 30EEC4B689 for ; Sat, 24 Oct 2015 05:39:50 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Gq3XBqELiL9t for ; Sat, 24 Oct 2015 05:39:50 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f42.google.com (mail-pa0-f42.google.com [209.85.220.42]) by theia.denx.de (Postfix) with ESMTPS id 5AE824B663 for ; Sat, 24 Oct 2015 05:39:39 +0200 (CEST) Received: by pasz6 with SMTP id z6so134099958pas.2 for ; Fri, 23 Oct 2015 20:39:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xJcBsEB+nbrIU/N2mCH9W1z38qbKoWqhIwqZetM3Slw=; b=C6JXXIjDsudOHVJ1OtwCW8sbHC458gnPEQmQ2rhDs6V91m7p0LTRyI+tBqgPoFKe05 De7B9MnbElPlSzrJoDVCGHKD6VeXIxSEaPGntJBpBnudkUnV9NAwg1t8n+4RKOGKKWaM 5nVO+aOwlMBPisEM32v/T1utQdEm98T7YUz1UxsZLxIIQ3pv1bX79QT5kHuXZbeHbddA +oWbk2mCwh1SoTf/bSk3AT/gTl4VMtMnQfaHdiNJteJDWa19oncyrblB/zDGNXhzI8r1 PT0IEjiXr0j+eQwMz5SQGcREa6o/TqyWayYbNZFXjoTOq9LBAgH9tO59vpjBsdxTz1zK do/Q== X-Received: by 10.68.137.161 with SMTP id qj1mr8971183pbb.154.1445657978377; Fri, 23 Oct 2015 20:39:38 -0700 (PDT) Received: from localhost.localdomain ([1.39.13.114]) by smtp.gmail.com with ESMTPSA id tk4sm21622200pab.45.2015.10.23.20.39.34 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 Oct 2015 20:39:37 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Sat, 24 Oct 2015 09:08:49 +0530 Message-Id: <1445657950-7117-3-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445657950-7117-1-git-send-email-jteki@openedev.com> References: <1445657950-7117-1-git-send-email-jteki@openedev.com> Cc: Jagan Teki , Siva Durga Prasad Paladugu , Michal Simek Subject: [U-Boot] [PATCH v5 02/23] spi: zynq_[q]spi: Use GENMASK macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" GENMASK macro used on zynq_spi.c and zynq_qspi.c GENMASK is used to create a contiguous bitmask([hi:lo]). Ex: (0x7 << 3) => GENMASK(5, 3) Cc: Siva Durga Prasad Paladugu Cc: Michal Simek Signed-off-by: Jagan Teki Acked-by: Siva Durga Prasad Paladugu --- drivers/spi/zynq_qspi.c | 8 ++++---- drivers/spi/zynq_spi.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index dd530a1..64b4eea 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */ #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */ #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */ -#define ZYNQ_QSPI_CR_FW_MASK (0x3 << 6) /* FIFO width */ -#define ZYNQ_QSPI_CR_SS_MASK (0xF << 10) /* Slave Select */ -#define ZYNQ_QSPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */ +#define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */ +#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */ #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */ #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ -#define ZYNQ_QSPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ /* zynq qspi Transmit Data Register */ diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 92e5712..9ede099 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -22,14 +22,14 @@ DECLARE_GLOBAL_DATA_PTR; /* zynq spi register bit masks ZYNQ_SPI___MASK */ #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ -#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ -#define ZYNQ_SPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */ +#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */ #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ -#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */