From patchwork Thu Oct 22 17:45:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 534523 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5182814131C for ; Fri, 23 Oct 2015 04:46:52 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 92B8DA74B7; Thu, 22 Oct 2015 19:46:47 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sOYU4_xnPnbD; Thu, 22 Oct 2015 19:46:47 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 23A7CA749D; Thu, 22 Oct 2015 19:46:47 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8AEB5A7479 for ; Thu, 22 Oct 2015 19:46:40 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9JgwniTDF1fI for ; Thu, 22 Oct 2015 19:46:40 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f54.google.com (mail-pa0-f54.google.com [209.85.220.54]) by theia.denx.de (Postfix) with ESMTPS id 114B3A746B for ; Thu, 22 Oct 2015 19:46:37 +0200 (CEST) Received: by padhk11 with SMTP id hk11so92561918pad.1 for ; Thu, 22 Oct 2015 10:46:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ODRt+uNY3VVrRorzDOLKqYt7jpjW9DZXhHPv4/ytqv0=; b=WPnrhotj1GV24MB4k3zy9uMrDVy8Z6d2EBKeB4jlGCMIJL7WBKVTC8DpEtI74TosPp DexPCBs9RY4YE1FLyMneT+IV4QwGBa3HJxZ5P7x7qUMznu7+w0tBqLSXSg5NhERJ9QmF 586l9XPUCt1Rs6Ifh8hF/wfp01zJjytb2myd6N8ojKTEkrXRLVNaiQtOA5es+IqENFc8 Ao/yxvQL0qwLLDu4F/B3RArTpWSGpQSGkKVstR+PN8CBVI3Lsi/CdQIbW1fuHSPyzXFJ t8LXLklYHLzXVtwwa7p4HP4Mo8BMNTfv9EPUwb5mNOHJGIrSP8Bc8EhLikJT5+/n2Wb/ TGeQ== X-Received: by 10.68.105.193 with SMTP id go1mr18524987pbb.59.1445535995694; Thu, 22 Oct 2015 10:46:35 -0700 (PDT) Received: from localhost.localdomain ([123.236.183.133]) by smtp.gmail.com with ESMTPSA id x6sm14878875pbt.3.2015.10.22.10.46.32 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 Oct 2015 10:46:34 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Thu, 22 Oct 2015 23:15:48 +0530 Message-Id: <1445535950-3473-2-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445535950-3473-1-git-send-email-jteki@openedev.com> References: <1445535950-3473-1-git-send-email-jteki@openedev.com> Cc: Jagan Teki , Tom Rini Subject: [U-Boot] [PATCH v3 2/4] spi: zynq_[q]spi: Use GENMASK macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" GENMASK macro used on zynq_spi.c and zynq_qspi.c GENMASK is used to create a contiguous bitmask([hi:lo]). Ex: (0x7 << 3) => GENMASK(5, 3) Cc: Tom Rini Signed-off-by: Jagan Teki --- Changes for v3, v2: - none drivers/spi/zynq_qspi.c | 8 ++++---- drivers/spi/zynq_spi.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index dd530a1..64b4eea 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */ #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */ #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */ -#define ZYNQ_QSPI_CR_FW_MASK (0x3 << 6) /* FIFO width */ -#define ZYNQ_QSPI_CR_SS_MASK (0xF << 10) /* Slave Select */ -#define ZYNQ_QSPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */ +#define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */ +#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */ #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */ #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ -#define ZYNQ_QSPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ /* zynq qspi Transmit Data Register */ diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 92e5712..9ede099 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -22,14 +22,14 @@ DECLARE_GLOBAL_DATA_PTR; /* zynq spi register bit masks ZYNQ_SPI___MASK */ #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ -#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ -#define ZYNQ_SPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */ +#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */ #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ -#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */