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BN3PR0301MB0867; 5:gqE0Zy1hzyKF3P5NLsf0iD8Zk9+dIWfzEY83WzYArLPObP0Yy9FtHdHm6Mn6QLP5W6zDFIlUgq81db/4/k/CYhVX7A5TbIibU29P0udALeX3sGY8SCV6BZhOMGoL21ZKYdWaot5Te+pjpXICbXDNxA==; 24:0nXVWwZeIBkc5SzizB5YBZBxrBAL0WLpPqw1kpNsRrVsAoW+Ssx3wOd/LEq4xunvjlRMECO7c1ew5d7KUVAr1CeSmKgrdDOv5YcQaDc5SR4=; 20:0vbCLAdQzTSZOOhEJLu47DLABFd9P6AcCVz5m7QE1+oIr9UkCDQZHNsQrf0TdxbJSb6AZLPKju1OzH+g8ZGILw== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2015 11:21:44.7438 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR0301MB0867 X-Mailman-Approved-At: Thu, 15 Oct 2015 14:00:59 +0200 Cc: u-boot@lists.denx.de, =?UTF-8?q?Horia=20Geant=C4=83?= Subject: [U-Boot] [PATCH v2] arm: ls102xa: enable snooping for CAAM transactions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable snooping for CAAM read & write transactions by programming the SCFG snoop configuration register: SCFG_SNPCNFGCR[SECRDSNP] SCFG_SNPCNFGCR[SECWRSNP] Signed-off-by: Horia Geantă Reviewed-by: Zhengxiong Jin --- v2 - moved initialization in arch_cpu_init (instead of board_early_init_f), as suggested by York. arch/arm/cpu/armv7/ls102xa/cpu.c | 3 +++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + 2 files changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 8dd95d98791d..0f10ed656af8 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -299,6 +299,7 @@ int arch_cpu_init(void) void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *rcpm2_base = (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; u32 state; /* @@ -326,6 +327,8 @@ int arch_cpu_init(void) */ fsl_epu_clean(epu_base); + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 60aa0d3b6f43..fbd06bafce31 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -144,6 +144,7 @@ struct ccsr_gur { }; #define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000