From patchwork Thu Oct 8 06:01:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 527617 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2DF2E140D72 for ; Thu, 8 Oct 2015 17:04:25 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 194604B869; Thu, 8 Oct 2015 08:04:22 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wWSa_fr-feCI; Thu, 8 Oct 2015 08:04:21 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 667904B854; Thu, 8 Oct 2015 08:04:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EE75C4B854 for ; Thu, 8 Oct 2015 08:04:17 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GBvPtcF6zaNi for ; Thu, 8 Oct 2015 08:04:17 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id 845FD4B84E for ; Thu, 8 Oct 2015 08:04:12 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id t9864Aib009960; Thu, 8 Oct 2015 01:04:10 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t9864ACs030130; Thu, 8 Oct 2015 01:04:10 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Thu, 8 Oct 2015 01:04:10 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t98647Dd010234; Thu, 8 Oct 2015 01:04:08 -0500 From: Lokesh Vutla To: Date: Thu, 8 Oct 2015 11:31:47 +0530 Message-ID: <1444284107-6352-1-git-send-email-lokeshvutla@ti.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 Cc: trini@konsulko.com, Sekhar Nori , Tero Kristo Subject: [U-Boot] [PATCH] ARM: k2e/l: Apply WA for selecting PA clock source X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" On keystone2 Lamarr and Edison platforms, the PA clocksource mux in PLL REG1, can be changed only after enabling its clock domain. So selecting the output of PASS PLL as input to PA only after enabling the clockdomain. This is as per the debug done by "Vitaly Andrianov " and based on the previous work done by "Hao Zhang " Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code") Reported-by: Vitaly Andrianov Tested-by: Vitaly Andrianov Signed-off-by: Lokesh Vutla --- arch/arm/mach-keystone/clock.c | 10 +++++++--- arch/arm/mach-keystone/include/mach/clock.h | 1 + board/ti/ks2_evm/board.c | 4 ++++ 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index fc3eadb..6cb6467 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -33,6 +33,11 @@ const struct keystone_pll_regs keystone_pll_regs[] = { [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, }; +inline void pll_pa_clk_sel(void) +{ + setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK); +} + static void wait_for_completion(const struct pll_init_data *data) { int i; @@ -180,9 +185,8 @@ void configure_secondary_pll(const struct pll_init_data *data) sdelay(21000); /* Select the Output of PASS PLL as input to PASS */ - if (data->pll == PASS_PLL) - setbits_le32(keystone_pll_regs[data->pll].reg1, - CFG_PLLCTL1_PAPLL_MASK); + if (data->pll == PASS_PLL && cpu_is_k2hk()) + pll_pa_clk_sel(); /* Select the Output of ARM PLL as input to ARM */ if (data->pll == TETRIS_PLL) diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index ddc5f8e..7e51702 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -118,6 +118,7 @@ unsigned long clk_round_rate(unsigned int clk, unsigned long hz); int clk_set_rate(unsigned int clk, unsigned long hz); int get_max_dev_speed(void); int get_max_arm_speed(void); +void pll_pa_clk_sel(void); #endif #endif diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 859a260..bee42bc 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -81,6 +82,9 @@ int board_eth_init(bd_t *bis) if (psc_enable_module(KS2_LPSC_CRYPTO)) return -1; + if (cpu_is_k2e() || cpu_is_k2l()) + pll_pa_clk_sel(); + port_num = get_num_eth_ports(); for (j = 0; j < port_num; j++) {