From patchwork Mon Sep 21 15:27:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 520344 X-Patchwork-Delegate: yamada.m@jp.panasonic.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 29B701401AD for ; Tue, 22 Sep 2015 01:29:39 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4A24F4B7EA; Mon, 21 Sep 2015 17:29:08 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id J-hnqOkBnyKu; Mon, 21 Sep 2015 17:29:08 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C762F4B83D; Mon, 21 Sep 2015 17:28:42 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D12D54B7DD for ; Mon, 21 Sep 2015 17:28:19 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0DJ5iyBY68JZ for ; Mon, 21 Sep 2015 17:28:19 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg009-v.nifty.com (conuserg009.nifty.com [202.248.44.35]) by theia.denx.de (Postfix) with ESMTPS id 27FBF4B7E8 for ; Mon, 21 Sep 2015 17:28:15 +0200 (CEST) Received: from grover.sesame (FL1-203-136-65-164.osk.mesh.ad.jp [203.136.65.164]) (authenticated) by conuserg009-v.nifty.com with ESMTP id t8LFRhfd030905; Tue, 22 Sep 2015 00:27:50 +0900 X-Nifty-SrcIP: [203.136.65.164] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Tue, 22 Sep 2015 00:27:36 +0900 Message-Id: <1442849262-26591-9-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442849262-26591-1-git-send-email-yamada.masahiro@socionext.com> References: <1442849262-26591-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH v2 08/14] ARM: uniphier: fix glitch signal problem for low-level debug X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently, IECTRL is enabled after pin-mux settings for the low-level debugging for PH1-LD4 and PH1-sLD8. While IECTRL is disabled, input signals are pulled-down, i.e. glitch signal (Low to High transition) problem occurs if pin-mux is set up first. As a result, one invalid character is input to the UART block and the auto-boot counting is terminated immediately. The correct initialization procedure is: [1] Enable IECTRL (if IECTRL exists for the pins) [2] Set up pin-muxing [3] Deassert the reset of the hardware block Currently, the low-level debugging is working for PH1-sLD3 and PH1-Pro4, but just in case, follow the sequence for all the SoCs. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S | 10 +++++----- arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S | 14 +++++++------- arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S | 6 +++--- arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S | 10 +++++----- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S index fd393dc..c0f14e0 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S +++ b/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S @@ -14,16 +14,16 @@ #include ENTRY(setup_lowlevel_debug) - init_debug_uart r0, r1, r2 + ldr r0, =SG_IECTRL + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] /* UART Port 0 */ sg_set_pinsel 85, 1, 8, 4, r0, r1 sg_set_pinsel 88, 1, 8, 4, r0, r1 - ldr r0, =SG_IECTRL - ldr r1, [r0] - orr r1, r1, #1 - str r1, [r0] + init_debug_uart r0, r1, r2 mov pc, lr ENDPROC(setup_lowlevel_debug) diff --git a/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S index ce5dd4b..56f3851 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S +++ b/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S @@ -15,13 +15,6 @@ #include ENTRY(setup_lowlevel_debug) - ldr r0, =SC_CLKCTRL - ldr r1, [r0] - orr r1, r1, #SC_CLKCTRL_CEN_PERI - str r1, [r0] - - init_debug_uart r0, r1, r2 - /* UART Port 0 */ sg_set_pinsel 127, 0, 4, 8, r0, r1 sg_set_pinsel 128, 0, 4, 8, r0, r1 @@ -30,5 +23,12 @@ ENTRY(setup_lowlevel_debug) mov r1, #1 str r1, [r0] + ldr r0, =SC_CLKCTRL + ldr r1, [r0] + orr r1, r1, #SC_CLKCTRL_CEN_PERI + str r1, [r0] + + init_debug_uart r0, r1, r2 + mov pc, lr ENDPROC(setup_lowlevel_debug) diff --git a/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S index ee2eae6..f4eccb4 100644 --- a/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S +++ b/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S @@ -15,6 +15,9 @@ #include ENTRY(setup_lowlevel_debug) + sg_set_pinsel 63, 0, 4, 4, r0, r1 + sg_set_pinsel 64, 1, 4, 4, r0, r1 + ldr r0, =BCSCR5 ldr r1, =0x24440000 str r1, [r0] @@ -26,8 +29,5 @@ ENTRY(setup_lowlevel_debug) init_debug_uart r0, r1, r2 - sg_set_pinsel 63, 0, 4, 4, r0, r1 - sg_set_pinsel 64, 1, 4, 4, r0, r1 - mov pc, lr ENDPROC(setup_lowlevel_debug) diff --git a/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S index 3ada4c9..571ce60 100644 --- a/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S +++ b/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S @@ -14,16 +14,16 @@ #include ENTRY(setup_lowlevel_debug) - init_debug_uart r0, r1, r2 + ldr r0, =SG_IECTRL + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] /* UART Port 0 */ sg_set_pinsel 70, 3, 8, 4, r0, r1 sg_set_pinsel 71, 3, 8, 4, r0, r1 - ldr r0, =SG_IECTRL - ldr r1, [r0] - orr r1, r1, #1 - str r1, [r0] + init_debug_uart r0, r1, r2 mov pc, lr ENDPROC(setup_lowlevel_debug)