From patchwork Thu Sep 10 20:55:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 516464 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 50BE914010F for ; Fri, 11 Sep 2015 07:13:44 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D9DF64B7B1; Thu, 10 Sep 2015 23:13:37 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id evSgVSNIxhbU; Thu, 10 Sep 2015 23:13:34 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EDF454B7E9; Thu, 10 Sep 2015 23:04:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2E1064B7C4 for ; Thu, 10 Sep 2015 22:56:42 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Q47Hlxrj87jE for ; Thu, 10 Sep 2015 22:56:42 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f174.google.com (mail-wi0-f174.google.com [209.85.212.174]) by theia.denx.de (Postfix) with ESMTPS id ECEF54B7D1 for ; Thu, 10 Sep 2015 22:55:36 +0200 (CEST) Received: by wicfx3 with SMTP id fx3so42363586wic.1 for ; Thu, 10 Sep 2015 13:55:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2kbKmf6RRx8HTsVWZ69dACxcV5MLifkH3kXxj1qny44=; b=QFir5o468MsW+pkxB2rpJjeFvzwh8vnsqcqXTdIQgb6IBZL3wWzM6koTJxmnSGJhsy JnlxnHg4zOnynrtbUeY2f1hmMMFQ6muq3Me3Ob4yxVWeRS8Ru22xGsAexKzLX/rACCdN aHkcUCEVjzR+06r21PPZYcPHk9dpT65j01wJysFhUBaYUJMwfNps+m5YzMma9COvDXjs aoSLrcLCF+R/atA/ODkJGVq5epEFqhzMGt9LTCcnBnflJcTh49Wu+JboS8vbRB9njtiC P5LKJbHuXwotp6dX1Xo+JuHP78xDOe9IURuXmOpMNVbDA6Mt/MU1gdu7lUekDRRoNTOR 72nQ== X-Gm-Message-State: ALoCoQmPFSS+3341Qj3jpoKhtmT6x63oQ0GOEcM3keXil40IwrCdn2xxRxnJEZekB1xREBoadLpF X-Received: by 10.194.103.228 with SMTP id fz4mr48937594wjb.53.1441918535815; Thu, 10 Sep 2015 13:55:35 -0700 (PDT) Received: from localhost.localdomain (cpc14-aztw22-2-0-cust189.18-1.cable.virginm.net. [82.45.1.190]) by smtp.gmail.com with ESMTPSA id s9sm17508216wjy.16.2015.09.10.13.55.34 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Sep 2015 13:55:35 -0700 (PDT) From: Peter Griffin To: u-boot@lists.denx.de, trini@konsulko.com, sjg@chromium.org, albert.u.boot@aribaud.net Date: Thu, 10 Sep 2015 21:55:18 +0100 Message-Id: <1441918518-25629-9-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441918518-25629-1-git-send-email-peter.griffin@linaro.org> References: <1441918518-25629-1-git-send-email-peter.griffin@linaro.org> Subject: [U-Boot] [PATCH v2 8/8] ARM: hikey: Adjust SDRAM_1_SIZE to 0x3EFFFFFF X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" DRAM region 0x3f000000 - 0x3fffffff is reserved for OP-TEE. Touching 0x3f000000 memory location from unsecure world causes the board to hang. Signed-off-by: Peter Griffin Reviewed-by: Simon Glass --- include/configs/hikey.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/hikey.h b/include/configs/hikey.h index b7c22e8..3af0213 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -42,7 +42,8 @@ #define PHYS_SDRAM_1 0x00000000 /* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ -#define PHYS_SDRAM_1_SIZE 0x3f000000 +#define PHYS_SDRAM_1_SIZE 0x3EFFFFFF + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000