From patchwork Thu Sep 3 11:43:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 513998 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B0F8A14029C for ; Thu, 3 Sep 2015 21:41:53 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=SPW2CmzP; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 416814B803; Thu, 3 Sep 2015 13:41:49 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mHhTqljMRmQL; Thu, 3 Sep 2015 13:41:49 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E3E7B4B7DC; Thu, 3 Sep 2015 13:41:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C4B384B768 for ; Thu, 3 Sep 2015 13:41:31 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id x1S-cptFtSvn for ; Thu, 3 Sep 2015 13:41:31 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f50.google.com (mail-pa0-f50.google.com [209.85.220.50]) by theia.denx.de (Postfix) with ESMTPS id 5A0E64B773 for ; Thu, 3 Sep 2015 13:41:28 +0200 (CEST) Received: by pacex6 with SMTP id ex6so39711516pac.0 for ; Thu, 03 Sep 2015 04:41:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=38BSYqMEc6IcSMw0daTxZ9KMZKacfCahoEaIEDJSFf4=; b=SPW2CmzPNHWByqHz8DLYd3lneJtG98oF3nL2Ct9+SILMHuBsWUIjZ7n8+pw4mfTk8q G1lUJuNQUi7rdumNYBwFu6X/w26E0vx8X4q3WJ6bdcsXtpTJkewd/AaG2+XHwRVl3MYe P/Lnchpy21YFk5chuHWRb+N3r9u2EX12tulfU21HuMNh/dWcYmfF9+qHeHzES5NVHri1 fH0KWNPP917/9yJvrvD9Vo9MYUC93M/St5kBtLgMoGYaygfQ3E1d6oIhb93WtSb0dKnS HMzsIQlk/vsTpaQ2bmZTZ5+GwwaO34SvwSwogQ2TbVcIXB0Rz74SetZ7FnPFoZUjTlzN 0MJQ== X-Received: by 10.66.227.98 with SMTP id rz2mr68166310pac.16.1441280486816; Thu, 03 Sep 2015 04:41:26 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id o3sm24849880pap.37.2015.09.03.04.41.26 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 03 Sep 2015 04:41:26 -0700 (PDT) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Thu, 3 Sep 2015 04:43:37 -0700 Message-Id: <1441280627-29714-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1441280627-29714-1-git-send-email-bmeng.cn@gmail.com> References: <1441280627-29714-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 01/11] x86: quark: Optimize MRC execution time X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Intel Quark SoC has a low end x86 processor with only 400MHz frequency. Currently it takes about 15 seconds for U-Boot to boot to shell and the most time consuming part is with MRC, which is about 12 seconds. MRC programs lots of registers on the SoC internal message bus indirectly accessed via pci bus. To speed up the boot, create an optimized version of pci config read/write dword routines which directly operate on PCI I/O ports. These two routines are inlined to provide better performance too. Now it only takes about 3 seconds to finish MRC, which is really fast (4 times faster than before). Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v3: None Changes in v2: - Drop v1 patch: "x86: quark: Make host bridge (b.d.f=0.0.0) visible", as pci_skip_dev() is not needed with the conversion to dm pci. - Drop v1 patch: "dm: pci: Allow skipping device configuration", as full PCIe root port support has been added and there is no need to add such feature at this point. We can still add such capability to dm pci in the future whenever needed. - Reorder to put patch "Optimize MRC execution time" as the first one in v2, as this patch addressed the slow boot time issue which exists before dm pci conversion, although it significantly improves more after dm pci conversion :-) - Move qrk_pci_write_config_dword() and qrk_pci_read_config_dword() to arch/x86/cpu/quark/quark.c - Rewrite this commit's message (ie: not mentioning dm pci conversion) arch/x86/cpu/quark/msg_port.c | 44 ++++++++++++++++----------------- arch/x86/include/asm/arch-quark/quark.h | 35 ++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 22 deletions(-) diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c index 31713e3..cf828f2 100644 --- a/arch/x86/cpu/quark/msg_port.c +++ b/arch/x86/cpu/quark/msg_port.c @@ -5,34 +5,34 @@ */ #include -#include #include #include +#include void msg_port_setup(int op, int port, int reg) { - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, - (((op) << 24) | ((port) << 16) | - (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE)); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, + (((op) << 24) | ((port) << 16) | + (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE)); } u32 msg_port_read(u8 port, u32 reg) { u32 value; - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, - reg & 0xffffff00); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); msg_port_setup(MSG_OP_READ, port, reg); - pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); + qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); return value; } void msg_port_write(u8 port, u32 reg, u32 value) { - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, - reg & 0xffffff00); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); msg_port_setup(MSG_OP_WRITE, port, reg); } @@ -40,19 +40,19 @@ u32 msg_port_alt_read(u8 port, u32 reg) { u32 value; - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, - reg & 0xffffff00); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); msg_port_setup(MSG_OP_ALT_READ, port, reg); - pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); + qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); return value; } void msg_port_alt_write(u8 port, u32 reg, u32 value) { - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, - reg & 0xffffff00); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); msg_port_setup(MSG_OP_ALT_WRITE, port, reg); } @@ -60,18 +60,18 @@ u32 msg_port_io_read(u8 port, u32 reg) { u32 value; - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, - reg & 0xffffff00); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); msg_port_setup(MSG_OP_IO_READ, port, reg); - pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); + qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); return value; } void msg_port_io_write(u8 port, u32 reg, u32 value) { - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, - reg & 0xffffff00); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); msg_port_setup(MSG_OP_IO_WRITE, port, reg); } diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index c997928..1ce5693 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -89,6 +89,41 @@ struct quark_rcba { u16 d20d21_ir; }; +#include +#include + +/** + * qrk_pci_read_config_dword() - Read a configuration value + * + * @dev: PCI device address: bus, device and function + * @offset: Dword offset within the device's configuration space + * @valuep: Place to put the returned value + * + * Note: This routine is inlined to provide better performance on Quark + */ +static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset, + u32 *valuep) +{ + outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); + *valuep = inl(PCI_REG_DATA); +} + +/** + * qrk_pci_write_config_dword() - Write a PCI configuration value + * + * @dev: PCI device address: bus, device and function + * @offset: Dword offset within the device's configuration space + * @value: Value to write + * + * Note: This routine is inlined to provide better performance on Quark + */ +static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset, + u32 value) +{ + outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); + outl(value, PCI_REG_DATA); +} + #endif /* __ASSEMBLY__ */ #endif /* _QUARK_H_ */