From patchwork Wed Sep 2 11:41:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joakim Tjernlund X-Patchwork-Id: 513502 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5A05E1401CD for ; Wed, 2 Sep 2015 21:47:11 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 819104B73A; Wed, 2 Sep 2015 13:47:06 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7XhlC7U2YRD2; Wed, 2 Sep 2015 13:47:06 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B71094B725; Wed, 2 Sep 2015 13:47:05 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3FD2E4B725 for ; Wed, 2 Sep 2015 13:47:03 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PeJYkgiFCK5h for ; Wed, 2 Sep 2015 13:47:03 +0200 (CEST) X-Greylist: delayed 354 seconds by postgrey-1.34 at theia; Wed, 02 Sep 2015 13:46:59 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp.transmode.se (smtp.transmode.se [31.15.61.139]) by theia.denx.de (Postfix) with ESMTP id 1342C4B71C for ; Wed, 2 Sep 2015 13:46:59 +0200 (CEST) Received: from gentoo-jocke.transmode.se (gentoo-jocke.transmode.se [172.20.4.10]) by smtp.transmode.se (Postfix) with ESMTP id 4994E1187172; Wed, 2 Sep 2015 13:41:05 +0200 (CEST) Received: from gentoo-jocke.transmode.se (localhost [127.0.0.1]) by gentoo-jocke.transmode.se (8.14.9/8.14.9) with ESMTP id t82Bf5O4028619; Wed, 2 Sep 2015 13:41:05 +0200 Received: (from jocke@localhost) by gentoo-jocke.transmode.se (8.14.9/8.14.9/Submit) id t82Bf4Ab028618; Wed, 2 Sep 2015 13:41:04 +0200 From: Joakim Tjernlund To: York Sun , u-boot@lists.denx.de Date: Wed, 2 Sep 2015 13:41:01 +0200 Message-Id: <1441194061-28527-1-git-send-email-joakim.tjernlund@transmode.se> X-Mailer: git-send-email 2.4.6 Subject: [U-Boot] [PATCH] Fix FSL DDR clock adjust calculation. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" T1040 RM specifies CLK_ADJUST as 5 bits starting at bit pos 9 in DDR_DDR_SDRAM_CLK_CNTL, update code to match. Signed-off-by: Joakim Tjernlund --- drivers/ddr/fsl/ctrl_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 3919257..57077e1 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1756,7 +1756,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, clk_adjust = popts->clk_adjust; ddr->ddr_sdram_clk_cntl = (0 | ((ss_en & 0x1) << 31) - | ((clk_adjust & 0xF) << 23) + | ((clk_adjust & 0x1F) << 22) ); debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); }