From patchwork Tue Sep 1 06:11:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 512699 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C78F01401E7 for ; Tue, 1 Sep 2015 16:12:39 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 79C964B80A; Tue, 1 Sep 2015 08:12:25 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bpM0GI5Na-O3; Tue, 1 Sep 2015 08:12:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ABA984B807; Tue, 1 Sep 2015 08:12:19 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AC0C04B810 for ; Tue, 1 Sep 2015 08:12:16 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BETtMUR8WWjX for ; Tue, 1 Sep 2015 08:12:16 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f43.google.com (mail-pa0-f43.google.com [209.85.220.43]) by theia.denx.de (Postfix) with ESMTPS id 0721A4B7F0 for ; Tue, 1 Sep 2015 08:12:10 +0200 (CEST) Received: by pacdd16 with SMTP id dd16so165065534pac.2 for ; Mon, 31 Aug 2015 23:12:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2U/1ne1opoFM3sXRNrMLN89NcywrnIh3QGVOHQqhjM4=; b=d03qLRLritbHnxLLbZqiM/is52q2Qn98x2SUKNCqaa8WLSnnjK6nOPbssGOOlJrMVV YTmLEf/jKeIIsSqnh+ffUSRUqgOtyOf7dTuwlkaWvIgxwDWna6JCftLIe/P9dAQSfV3o FnRe13lgQQHoLOSlx59GWsBcLRnuchUhAstjgSjKYHQazBbcYNPC541IqVh+nQ7q21tC hyiTWfUpikx/JfYVF2ZkrjnWUhjW5VrDI0Gje8XTlETnZqhEk3g9acijHMZ3RFH5wdBG mb0PuQsHMWutJF3jUqhpA5Y7KjYNfDh/iSsLozj8/zcWOkipaph5TZJtucGMCjIqwIsz B6KQ== X-Received: by 10.68.93.133 with SMTP id cu5mr44094937pbb.71.1441087929570; Mon, 31 Aug 2015 23:12:09 -0700 (PDT) Received: from Jubuntu.amcc.com ([182.73.239.130]) by smtp.gmail.com with ESMTPSA id pi4sm16672144pdb.60.2015.08.31.23.12.06 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 31 Aug 2015 23:12:08 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Tue, 1 Sep 2015 11:41:34 +0530 Message-Id: <1441087907-25993-4-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441087907-25993-1-git-send-email-jteki@openedev.com> References: <1441087907-25993-1-git-send-email-jteki@openedev.com> Cc: Jagan Teki , Michal Simek , Siva Durga Prasad Paladugu Subject: [U-Boot] [PATCH v4 03/16] doc: device-tree-bindings: spi: Add zynq qspi info X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Added device-tree-binding information for zynq qspi controller driver. Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Tested-by: Jagan Teki --- doc/device-tree-bindings/spi/spi-zynq-qspi.txt | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-zynq-qspi.txt diff --git a/doc/device-tree-bindings/spi/spi-zynq-qspi.txt b/doc/device-tree-bindings/spi/spi-zynq-qspi.txt new file mode 100644 index 0000000..47472fd --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-zynq-qspi.txt @@ -0,0 +1,26 @@ +Xilinx Zynq QSPI controller Device Tree Bindings +------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,zynq-qspi-1.0". +- reg : Physical base address and size of QSPI registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller +- clock-names : List of input clock names - "ref_clk", "pclk" + (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). + +Optional properties: +- num-cs : Number of chip selects used. + +Example: + qspi@e000d000 { + compatible = "xlnx,zynq-qspi-1.0"; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 10>, <&clkc 43>; + interrupt-parent = <&intc>; + interrupts = <0 19 4>; + num-cs = <1>; + reg = <0xe000d000 0x1000>; + } ;