From patchwork Tue Sep 1 06:11:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 512712 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 8CB031401E7 for ; Tue, 1 Sep 2015 16:14:41 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D5D644B8D0; Tue, 1 Sep 2015 08:13:28 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id czmMDz42tsxh; Tue, 1 Sep 2015 08:13:28 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8D3064B8B9; Tue, 1 Sep 2015 08:13:17 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8770E4B8D1 for ; Tue, 1 Sep 2015 08:13:15 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3gxaRwPsyiRZ for ; Tue, 1 Sep 2015 08:13:15 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f41.google.com (mail-pa0-f41.google.com [209.85.220.41]) by theia.denx.de (Postfix) with ESMTPS id 644484B876 for ; Tue, 1 Sep 2015 08:12:55 +0200 (CEST) Received: by pacgr6 with SMTP id gr6so14369353pac.3 for ; Mon, 31 Aug 2015 23:12:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6cvCsycPLwmHoGagtuM2v2FzDdLSYAzCo/J9+DATdbU=; b=AjlYJzfgB+Y0W0dwz37AW0BNlKgevi8G/joEaqcI9zhvAoXFmiLpsF4FmzkQBM9977 51DC5ID+uO9f41DDW7IL+NhYHWvhi8fr9djPa3Zp0h5VlehT2adAxe0sHDDAOadLDanW xGouE+ivGkPZaDl8c8RBjzt2MTtoGphcKJ553nzageo96xcHURruYmR7/fOZ5OOR7NfQ r+aQThvo97fShai60KvheZbdeJwb+FASMRVu3aywEX2SECp6vXHbs3CrhUoukHXvt6jc mG05IZ9aDIhCUaMmdPxSMucGRSVFTvJpfTQTV9aPyVxHsbhh8FhomuLSljKQyWaPMOkK LvJw== X-Received: by 10.69.11.5 with SMTP id ee5mr43677207pbd.89.1441087973987; Mon, 31 Aug 2015 23:12:53 -0700 (PDT) Received: from Jubuntu.amcc.com ([182.73.239.130]) by smtp.gmail.com with ESMTPSA id pi4sm16672144pdb.60.2015.08.31.23.12.49 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 31 Aug 2015 23:12:52 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Tue, 1 Sep 2015 11:41:47 +0530 Message-Id: <1441087907-25993-17-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441087907-25993-1-git-send-email-jteki@openedev.com> References: <1441087907-25993-1-git-send-email-jteki@openedev.com> Cc: Jagan Teki Subject: [U-Boot] [PATCH v4 16/16] spi: zynq_spi: Store cs value into private data X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Store cs value into private data and use it while activating chipselect instead of passing through function. Signed-off-by: Jagan Teki --- drivers/spi/zynq_spi.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 70d7716..70ddd7f 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -61,6 +61,7 @@ struct zynq_spi_platdata { /* zynq spi priv */ struct zynq_spi_priv { struct zynq_spi_regs *regs; + u8 cs; u8 mode; u8 fifo_depth; u32 freq; /* required frequency */ @@ -128,7 +129,7 @@ static int zynq_spi_probe(struct udevice *bus) return 0; } -static void spi_cs_activate(struct udevice *dev, uint cs) +static void spi_cs_activate(struct udevice *dev) { struct udevice *bus = dev->parent; struct zynq_spi_priv *priv = dev_get_priv(bus); @@ -143,7 +144,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs) * xx01 - cs1 * x011 - cs2 */ - cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; writel(cr, ®s->cr); } @@ -199,8 +200,9 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen, return -1; } + priv->cs = slave_plat->cs; if (flags & SPI_XFER_BEGIN) - spi_cs_activate(dev, slave_plat->cs); + spi_cs_activate(dev); while (rx_len > 0) { /* Write the data into TX FIFO - tx threshold is fifo_depth */