diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2636db3..0ab0c24 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -69,10 +69,6 @@ choice
 config ARCH_AT91
 	bool "Atmel AT91"
 
-config TARGET_SCB9328
-	bool "Support scb9328"
-	select CPU_ARM920T
-
 config TARGET_VCMA9
 	bool "Support VCMA9"
 	select CPU_ARM920T
@@ -874,7 +870,6 @@ source "board/phytec/pcm051/Kconfig"
 source "board/ppcag/bg0900/Kconfig"
 source "board/samsung/smdk2410/Kconfig"
 source "board/sandisk/sansa_fuze_plus/Kconfig"
-source "board/scb9328/Kconfig"
 source "board/schulercontrol/sc_sps_1/Kconfig"
 source "board/siemens/draco/Kconfig"
 source "board/siemens/pxm2/Kconfig"
diff --git a/board/scb9328/Kconfig b/board/scb9328/Kconfig
deleted file mode 100644
index 68e99ea..0000000
--- a/board/scb9328/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_SCB9328
-
-config SYS_BOARD
-	default "scb9328"
-
-config SYS_SOC
-	default "imx"
-
-config SYS_CONFIG_NAME
-	default "scb9328"
-
-endif
diff --git a/board/scb9328/MAINTAINERS b/board/scb9328/MAINTAINERS
deleted file mode 100644
index 0917266..0000000
--- a/board/scb9328/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SCB9328 BOARD
-M:	Torsten Koschorrek <koschorrek@synertronixx.de>
-S:	Maintained
-F:	board/scb9328/
-F:	include/configs/scb9328.h
-F:	configs/scb9328_defconfig
diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile
deleted file mode 100644
index 0b08f1a..0000000
--- a/board/scb9328/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= scb9328.o flash.o
-obj-y	+= lowlevel_init.o
diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c
deleted file mode 100644
index 73bfa00..0000000
--- a/board/scb9328/flash.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This code was inspired by Marius Groeger and Kyle Harris code
- * available in other board ports for U-Boot
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- */
-
-#include <common.h>
-#include "intel.h"
-
-
-/*
- * This code should handle CFI FLASH memory device. This code is very
- * minimalistic approach without many essential error handling code as well.
- * Because U-Boot actually is missing smart handling of FLASH device,
- * we just set flash_id to anything else to FLASH_UNKNOW, so common code
- * can call us without any restrictions.
- * TODO: Add CFI Query, to be able to determine FLASH device.
- * TODO: Add error handling code
- * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
- *       hopefully may work with other configurations.
- */
-
-#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
-#  define FLASH_BUS vu_char
-#  define FLASH_BUS_RET u_char
-#  if ( SCB9328_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  else
-#    error "With 8bit bus only one chip is allowed"
-#  endif
-
-
-#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
-#  define FLASH_BUS vu_short
-#  define FLASH_BUS_RET u_short
-#  if ( SCB9328_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  elif ( SCB9328_FLASH_INTERLEAVE == 2 )
-#    define FLASH_CMD( x ) (( x << 8 )| x )
-#  else
-#    error "With 16bit bus only 1 or 2 chip(s) are allowed"
-#  endif
-
-
-#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
-#  define FLASH_BUS vu_long
-#  define FLASH_BUS_RET u_long
-#  if ( SCB9328_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  elif ( SCB9328_FLASH_INTERLEAVE == 2 )
-#    define FLASH_CMD( x ) (( x << 16 )| x )
-#  elif ( SCB9328_FLASH_INTERLEAVE == 4 )
-#    define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
-#  else
-#    error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
-#  endif
-
-#else
-#  error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
-#endif
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static FLASH_BUS_RET flash_status_reg (void)
-{
-
-	FLASH_BUS *addr = (FLASH_BUS *) 0;
-
-	/* cppcheck-suppress nullPointer */
-	*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
-
-	/* cppcheck-suppress nullPointer */
-	return *addr;
-}
-
-static int flash_ready (ulong timeout)
-{
-	int ok = 1;
-	ulong start;
-
-	start = get_timer(0);
-	while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
-		   FLASH_CMD (CFI_INTEL_SR_READY)) {
-		if (get_timer(start) > timeout && timeout != 0) {
-			ok = 0;
-			break;
-		}
-	}
-	return ok;
-}
-
-#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
-#  error "SCB9328 platform has only one flash bank!"
-#endif
-
-
-ulong flash_init (void)
-{
-	int i;
-	unsigned long address = SCB9328_FLASH_BASE;
-
-	flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
-	flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	flash_info[0].flash_id = INTEL_MANUFACT;
-	memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
-		flash_info[0].start[i] = address;
-#ifdef SCB9328_FLASH_UNLOCK
-		/* Some devices are hw locked after start. */
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
-		flash_ready (0);
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-#endif
-		address += SCB9328_FLASH_SECT_SIZE;
-	}
-
-	flash_protect (FLAG_PROTECT_SET,
-				   CONFIG_SYS_FLASH_BASE,
-				   CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-				   &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-				   CONFIG_ENV_ADDR,
-				   CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return SCB9328_FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	printf (" Intel vendor\n");
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; i++) {
-		if (!(i % 5)) {
-			printf ("\n");
-		}
-
-		printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-}
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, non_protected = 0, sector;
-	int rc = ERR_OK;
-
-	FLASH_BUS *address;
-
-	for (sector = s_first; sector <= s_last; sector++) {
-		if (!info->protect[sector]) {
-			non_protected++;
-		}
-	}
-
-	if (!non_protected) {
-		return ERR_PROTECTED;
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	flag = disable_interrupts ();
-
-
-	/* Start erase on unprotected sectors */
-	for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
-		if (info->protect[sector]) {
-			printf ("Protected sector %2d skipping...\n", sector);
-			continue;
-		} else {
-			printf ("Erasing sector %2d ... ", sector);
-		}
-
-		address = (FLASH_BUS *) (info->start[sector]);
-
-		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
-		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
-		if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
-			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
-			printf ("ok.\n");
-		} else {
-			*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
-			rc = ERR_TIMOUT;
-			printf ("timeout! Aborting...\n");
-			break;
-		}
-		*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-	}
-	if (ctrlc ())
-		printf ("User Interrupt!\n");
-
-	/* allow flash to settle - wait 10 ms */
-	udelay_masked (10000);
-	if (flag) {
-		enable_interrupts ();
-	}
-
-	return rc;
-}
-
-static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
-{
-	FLASH_BUS *address = (FLASH_BUS *) dest;
-	int rc = ERR_OK;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*address & data) != data) {
-		return ERR_NOT_ERASED;
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-
-	flag = disable_interrupts ();
-
-	*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
-	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
-	*address = data;
-
-	if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
-		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
-		rc = ERR_TIMOUT;
-		printf ("timeout! Aborting...\n");
-	}
-
-	*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-	if (flag) {
-		enable_interrupts ();
-	}
-
-	return rc;
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong read_addr, write_addr;
-	FLASH_BUS data;
-	int i, result = ERR_OK;
-
-
-	read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
-	write_addr = read_addr;
-	if (read_addr != addr) {
-		data = 0;
-		for (i = 0; i < sizeof (FLASH_BUS); i++) {
-			if (read_addr < addr || cnt == 0) {
-				data |= *((uchar *) read_addr) << i * 8;
-			} else {
-				data |= (*src++) << i * 8;
-				cnt--;
-			}
-			read_addr++;
-		}
-		if ((result = write_data (info, write_addr, data)) != ERR_OK) {
-			return result;
-		}
-		write_addr += sizeof (FLASH_BUS);
-	}
-	for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
-		if ((result = write_data (info, write_addr,
-								  *((FLASH_BUS *) src))) != ERR_OK) {
-			return result;
-		}
-		write_addr += sizeof (FLASH_BUS);
-		src += sizeof (FLASH_BUS);
-	}
-	if (cnt > 0) {
-		read_addr = write_addr;
-		data = 0;
-		for (i = 0; i < sizeof (FLASH_BUS); i++) {
-			if (cnt > 0) {
-				data |= (*src++) << i * 8;
-				cnt--;
-			} else {
-				data |= *((uchar *) read_addr) << i * 8;
-			}
-			read_addr++;
-		}
-		if ((result = write_data (info, write_addr, data)) != 0) {
-			return result;
-		}
-	}
-	return ERR_OK;
-}
diff --git a/board/scb9328/intel.h b/board/scb9328/intel.h
deleted file mode 100644
index 5596d27..0000000
--- a/board/scb9328/intel.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * SPDX-License-Identifier:	BSD-3-Clause
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef	FLASH_INTEL_H
-#define	FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define	CFI_CHIP_INTEL_28F320J3A		0x0016
-#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
-#define	CFI_CHIP_INTEL_28F640J3A		0x0017
-#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
-#define	CFI_CHIP_INTEL_28F128J3A		0x0018
-#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define	CFI_CHIP_INTEL_28F640K3			0x8801
-#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
-#define	CFI_CHIP_INTEL_28F128K3			0x8802
-#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
-#define	CFI_CHIP_INTEL_28F256K3			0x8803
-#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
-#define	CFI_CHIP_INTEL_28F640K18		0x8805
-#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
-#define	CFI_CHIP_INTEL_28F128K18		0x8806
-#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
-#define	CFI_CHIP_INTEL_28F256K18		0x8807
-#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
-
-#endif /* FLASH_INTEL_H */
diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S
deleted file mode 100644
index d572724..0000000
--- a/board/scb9328/lowlevel_init.S
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-/* Change PERCLK1DIV to 14 ie 14+1 */
-	ldr		r0,	=PCDR
-	ldr		r1,	=CONFIG_SYS_PCDR_VAL
-	str		r1,   [r0]
-
-/* set MCU PLL Control Register 0 */
-
-	ldr		r0,	=MPCTL0
-	ldr		r1,	=CONFIG_SYS_MPCTL0_VAL
-	str		r1,   [r0]
-
-/* set mpll restart bit */
-	ldr		r0, =CSCR
-	ldr		r1, [r0]
-	orr		r1,r1,#(1<<21)
-	str		r1, [r0]
-
-	mov		r2,#0x10
-1:
-	mov		r3,#0x2000
-2:
-	subs	r3,r3,#1
-	bne		2b
-
-	subs	r2,r2,#1
-	bne		1b
-
-/* set System PLL Control Register 0 */
-
-	ldr		r0,	=SPCTL0
-	ldr		r1,	=CONFIG_SYS_SPCTL0_VAL
-	str		r1,   [r0]
-
-/* set spll restart bit */
-	ldr		r0, =CSCR
-	ldr		r1, [r0]
-	orr		r1,r1,#(1<<22)
-	str		r1, [r0]
-
-	mov		r2,#0x10
-1:
-	mov		r3,#0x2000
-2:
-	subs	r3,r3,#1
-	bne		2b
-
-	subs	r2,r2,#1
-	bne		1b
-
-	ldr		r0,   =CSCR
-	ldr		r1,   =CONFIG_SYS_CSCR_VAL
-	str		r1,   [r0]
-
-/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
- *this.....
- *
- * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
- * register 1, this stops it using the output of the PLL and thus runs at the
- * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
- * use the value set in the CM_OSC registers...regardless of what you set it
- * too!  Thus, although i thought i was running at 140MHz, i'm actually running
- * at 40!..
-
- * Slapping this into my bootloader does the trick...
-
- * MRC p15,0,r0,c1,c0,0    ; read core configuration register
- * ORR r0,r0,#0xC0000000   ; set asynchronous clocks and not fastbus mode
- * MCR p15,0,r0,c1,c0,0    ; write modified value to core configuration
- * register
- */
-	MRC p15,0,r0,c1,c0,0
-	ORR r0,r0,#0xC0000000
-	MCR p15,0,r0,c1,c0,0
-
-	ldr		r0,	=GPR(0)
-	ldr		r1,	=CONFIG_SYS_GPR_A_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GIUS(0)
-	ldr		r1,	=CONFIG_SYS_GIUS_A_VAL
-	str		r1,   [r0]
-
-/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
-
-	ldr		r0,	=FMCR
-	ldr		r1,	=CONFIG_SYS_FMCR_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS0U
-	ldr		r1,	=CONFIG_SYS_CS0U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS0L
-	ldr		r1,	=CONFIG_SYS_CS0L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS1U
-	ldr		r1,	=CONFIG_SYS_CS1U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS1L
-	ldr		r1,	=CONFIG_SYS_CS1L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS2U
-	ldr		r1,	=CONFIG_SYS_CS2U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS2L
-	ldr		r1,	=CONFIG_SYS_CS2L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS3U
-	ldr		r1,	=CONFIG_SYS_CS3U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS3L
-	ldr		r1,	=CONFIG_SYS_CS3L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS4U
-	ldr		r1,	=CONFIG_SYS_CS4U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS4L
-	ldr		r1,	=CONFIG_SYS_CS4L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS5U
-	ldr		r1,	=CONFIG_SYS_CS5U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=CS5L
-	ldr		r1,	=CONFIG_SYS_CS5L_VAL
-	str		r1,   [r0]
-
-/* SDRAM Setup */
-
-	ldr		r0, =SDCTL0
-	ldr		r1, =PRECHARGE_CMD
-	str		r1,   [r0]
-
-	ldr		r0, =0x08200000
-	ldr		r1, =0x0 /* Issue Precharge all Command */
-	str		r1,   [r0]
-
-	ldr		r0, =SDCTL0
-	ldr		r1, =AUTOREFRESH_CMD
-	str		r1,   [r0]
-
-	ldr		r0, =0x08000000
-	ldr		r1, =0x0 /* Issue AutoRefresh Command */
-	str		r1,   [r0]
-	str		r1,   [r0]
-	str		r1,   [r0]
-	str		r1,   [r0]
-	str		r1,   [r0]
-	str		r1,   [r0]
-	str		r1,   [r0]
-	str		r1,   [r0]
-
-	ldr		r0, =SDCTL0
-	ldr		r1, =0xb10a8300
-	str		r1,   [r0]
-
-	ldr		r0, =0x08223000 /* CAS Latency 2 */
-	ldr		r1, =0x0   /* Issue Mode Register Command, Burst Length = 8 */
-	str		r1,   [r0]
-
-	ldr		r0, =SDCTL0
-	ldr		r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
-	str		r1,   [r0]
-
-	mov	pc,r10
diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c
deleted file mode 100644
index 3463f52..0000000
--- a/board/scb9328/scb9328.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init (void)
-{
-	gd->bd->bi_arch_number = MACH_TYPE_SCB9328;
-	gd->bd->bi_boot_params = 0x08000100;
-
-	return 0;
-}
-
-int dram_init (void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)SCB9328_SDRAM_1,
-				    SCB9328_SDRAM_1_SIZE);
-
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
-	gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
-}
-
-/**
- * show_boot_progress: - indicate state of the boot process
- *
- * @param status: Status number - see README for details.
- *
- * The CSB226 does only have 3 LEDs, so we switch them on at the most
- * important states (1, 5, 15).
- */
-
-void show_boot_progress (int status)
-{
-	return;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
-	return dm9000_initialize(bis);
-}
-#endif
diff --git a/configs/scb9328_defconfig b/configs/scb9328_defconfig
deleted file mode 100644
index c9c5034..0000000
--- a/configs/scb9328_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_SCB9328=y
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="scb9328> "
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
deleted file mode 100644
index d4ffb46..0000000
--- a/include/configs/scb9328.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- * 2003/13/06 Initial MP10 Support copied from wepep250
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IMX		1     /* This is a Motorola MC9328MXL Chip */
-#define CONFIG_SCB9328		1     /* on a scb9328tronix board */
-
-#define CONFIG_IMX_SERIAL
-#define CONFIG_IMX_SERIAL1
-/*
- * Select serial console configuration
- */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-/*
- * Boot options. Setting delay to -1 stops autostart count down.
- * NOTE: Sending parameters to kernel depends on kernel version and
- * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
- * parameters at all! Do not get confused by them so.
- */
-#define CONFIG_BOOTDELAY   -1
-#define CONFIG_BOOTARGS	   "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
-#define CONFIG_BOOTCOMMAND "bootm 10040000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		10.10.10.9
-#define CONFIG_SERVERIP		10.10.10.10
-
-/*
- * General options for u-boot. Modify to save memory foot print
- */
-#define CONFIG_SYS_LONGHELP				      /* undef saves memory  */
-#define CONFIG_SYS_CBSIZE		256		      /* console I/O buffer  */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size   */
-#define CONFIG_SYS_MAXARGS		16		      /* max command args    */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	      /* boot args buf size  */
-
-#define CONFIG_SYS_MEMTEST_START	0x08100000	      /* memtest test area   */
-#define CONFIG_SYS_MEMTEST_END		0x08F00000
-
-#define CONFIG_SYS_CPUSPEED		0x141	     /* core clock - register value  */
-
-#define CONFIG_BAUDRATE 115200
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
-#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
-#define CONFIG_INITRD_TAG	     1	 /* send initrd params		     */
-
-/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128<<10) )
-
-/* SDRAM Setup Values
-0x910a8300 Precharge Command CAS 3
-0x910a8200 Precharge Command CAS 2
-
-0xa10a8300 AutoRefresh Command CAS 3
-0xa10a8200 Set AutoRefresh Command CAS 2 */
-
-#define PRECHARGE_CMD 0x910a8200
-#define AUTOREFRESH_CMD 0xa10a8200
-
-/*
- * SDRAM Memory Map
- */
-/* SH FIXME */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of SDRAM */
-#define SCB9328_SDRAM_1		0x08000000	/* SDRAM bank #1	   */
-#define SCB9328_SDRAM_1_SIZE	0x01000000	/* 16 MB		   */
-
-#define CONFIG_SYS_TEXT_BASE	0x10000000
-
-#define CONFIG_SYS_SDRAM_BASE	SCB9328_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR	(SCB9328_SDRAM_1 + 0xf00000)
-
-/*
- * Configuration for FLASH memory for the Synertronixx board
- */
-
-/* #define SCB9328_FLASH_32M */
-
-/* 32MB */
-#ifdef SCB9328_FLASH_32M
-#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
-#define CONFIG_SYS_MAX_FLASH_SECT		256	/* number of sector in FLASH bank    */
-#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
-#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
-#define SCB9328_FLASH_BANK_SIZE	 0x02000000	/* size of one flash bank	     */
-#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
-#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
-#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
-#else
-
-/* 16MB */
-#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
-#define CONFIG_SYS_MAX_FLASH_SECT		128	/* number of sector in FLASH bank    */
-#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
-#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
-#define SCB9328_FLASH_BANK_SIZE	 0x01000000	/* size of one flash bank	     */
-#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
-#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
-#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
-#endif /* SCB9328_FLASH_32M */
-
-/* This should be defined if CFI FLASH device is present. Actually benefit
-   is not so clear to me. In other words we can provide more informations
-   to user, but this expects more complex flash handling we do not provide
-   now.*/
-#undef	CONFIG_SYS_FLASH_CFI
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000    /* timeout for Erase operation */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	240000    /* timeout for Write operation */
-
-#define CONFIG_SYS_FLASH_BASE		SCB9328_FLASH_BASE
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * Right now there is no gain for user, but later on booting kernel might be
- * possible. Consider using XIP kernel running from flash to save RAM
- * footprint.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#define CONFIG_SYS_JFFS2_FIRST_BANK		0
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR		5
-#define CONFIG_SYS_JFFS2_NUM_BANKS		1
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-/* Setup for PA23 which is Reset Default PA23 but has to become
-   CS5 */
-
-#define CONFIG_SYS_GPR_A_VAL		0x00800000
-#define CONFIG_SYS_GIUS_A_VAL		0x0043fffe
-
-#define CONFIG_SYS_MONITOR_BASE	0x10000000
-#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )  */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0x10020000	/* absolute address for now  */
-#define CONFIG_ENV_SIZE		0x20000
-
-#define	 CONFIG_ENV_OVERWRITE  1		/* env is not writable now   */
-
-/*
- * CSxU_VAL:
- * 63| x	x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
- *   |DTACK_SEL|0|BCD |	  BCS	| PSZ|PME|SYNC|	 DOL	| CNC|	  WSC	    | 0| WWS  |	  EDC  |
- *
- * CSxL_VAL:
- * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x	 x x | x x  x	 x| 0
- *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
- */
-
-#define CONFIG_SYS_CS0U_VAL 0x000F2000
-#define CONFIG_SYS_CS0L_VAL 0x11110d01
-#define CONFIG_SYS_CS1U_VAL 0x000F0a00
-#define CONFIG_SYS_CS1L_VAL 0x11110601
-#define CONFIG_SYS_CS2U_VAL 0x0
-#define CONFIG_SYS_CS2L_VAL 0x0
-
-#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
-#define CONFIG_SYS_CS3L_VAL 0x00000303
-
-#define CONFIG_SYS_CS4U_VAL 0x000F0a00
-#define CONFIG_SYS_CS4L_VAL 0x11110301
-
-/* CNC == 3 too long
-   #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
-
-/* #define CONFIG_SYS_CS5U_VAL 0x00008400
-   mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
-   kaum langsamer ist */
-/* #define CONFIG_SYS_CS5U_VAL 0x00009400
-   #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
-
-#define CONFIG_SYS_CS5U_VAL 0x00008400
-#define CONFIG_SYS_CS5L_VAL 0x00000D03
-
-#define CONFIG_DRIVER_DM9000		1
-#define CONFIG_DM9000_BASE		0x16000000
-#define DM9000_IO			CONFIG_DM9000_BASE
-#define DM9000_DATA			(CONFIG_DM9000_BASE+4)
-
-/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
-   f_ref=16,777MHz
-
-   0x002a141f: 191,9944MHz
-   0x040b2007: 144MHz
-   0x042a141f: 96MHz
-   0x0811140d: 64MHz
-   0x040e200e: 150MHz
-   0x00321431: 200MHz
-
-   0x08001800: 64MHz mit 16er Quarz
-   0x04001800: 96MHz mit 16er Quarz
-   0x04002400: 144MHz mit 16er Quarz
-
-   31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
-      |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|	    */
-
-#define CPU200
-
-#ifdef CPU200
-#define CONFIG_SYS_MPCTL0_VAL 0x00321431
-#else
-#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
-#endif
-
-/* #define BUS64 */
-#define BUS72
-
-#ifdef BUS72
-#define CONFIG_SYS_SPCTL0_VAL 0x04002400
-#endif
-
-#ifdef BUS96
-#define CONFIG_SYS_SPCTL0_VAL 0x04001800
-#endif
-
-#ifdef BUS64
-#define CONFIG_SYS_SPCTL0_VAL 0x08001800
-#endif
-
-/* Das ist der BCLK Divider, der aus der System PLL
-   BCLK und HCLK erzeugt:
-   31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
-   0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
-   0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
-   0x2f001003 : 192MHz/5=38,4MHz
-   0x2f000003 : 64MHz/1
-   Bit 22: SPLL Restart
-   Bit 21: MPLL Restart */
-
-#ifdef BUS64
-#define CONFIG_SYS_CSCR_VAL 0x2f030003
-#endif
-
-#ifdef BUS72
-#define CONFIG_SYS_CSCR_VAL 0x2f030403
-#endif
-
-/*
- * Well this has to be defined, but on the other hand it is used differently
- * one may expect. For instance loadb command do not cares :-)
- * So advice is - do not relay on this...
- */
-#define CONFIG_SYS_LOAD_ADDR 0x08400000
-
-#define MHZ16QUARZINUSE
-
-#ifdef MHZ16QUARZINUSE
-#define CONFIG_SYSPLL_CLK_FREQ 16000000
-#else
-#define CONFIG_SYSPLL_CLK_FREQ 16780000
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 16780000
-
-/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
-#define CONFIG_SYS_FMCR_VAL 0x00000001
-
-/* Bit[0:3] contain PERCLK1DIV for UART 1
-   0x000b00b ->b<- -> 192MHz/12=16MHz
-   0x000b00b ->8<- -> 144MHz/09=16MHz
-   0x000b00b ->3<- -> 64MHz/4=16MHz */
-
-#ifdef BUS96
-#define CONFIG_SYS_PCDR_VAL 0x000b00b5
-#endif
-
-#ifdef BUS64
-#define CONFIG_SYS_PCDR_VAL 0x000b00b3
-#endif
-
-#ifdef BUS72
-#define CONFIG_SYS_PCDR_VAL 0x000b00b8
-#endif
-
-#endif	/* __CONFIG_H */
