From patchwork Mon Aug 17 14:24:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 507988 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3266C1400A0 for ; Tue, 18 Aug 2015 00:27:11 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C17E14B8EC; Mon, 17 Aug 2015 16:27:04 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bQ_MejW-bFbr; Mon, 17 Aug 2015 16:27:04 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A6EF74B8ED; Mon, 17 Aug 2015 16:26:59 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D13304B8C6 for ; Mon, 17 Aug 2015 16:26:55 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9Pt2Bb_YwCd9 for ; Mon, 17 Aug 2015 16:26:55 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 5A7C24B8C3 for ; Mon, 17 Aug 2015 16:26:52 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t7HEQoS6020212 for ; Mon, 17 Aug 2015 09:26:50 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t7HEQoG2008340 for ; Mon, 17 Aug 2015 09:26:50 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Mon, 17 Aug 2015 09:26:49 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t7HEQiOT024635; Mon, 17 Aug 2015 09:26:47 -0500 From: Lokesh Vutla To: , , Date: Mon, 17 Aug 2015 19:54:48 +0530 Message-ID: <1439821492-32615-2-git-send-email-lokeshvutla@ti.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1439821492-32615-1-git-send-email-lokeshvutla@ti.com> References: <1439821492-32615-1-git-send-email-lokeshvutla@ti.com> MIME-Version: 1.0 Cc: t-kristo@ti.com, nsekhar@ti.com Subject: [U-Boot] [PATCH 1/5] ARM: keystone2: configs: Move SP to end of u-boot section X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently u-boot stack is defined at the beginning of MSMC RAM. This is a problem for uart boot mode as ROM downloads directly to starting of MSMC RAM. Fixing it by moving stack to the end of u-boot section and shifting SYS_TEXT_BASE to the start of MSMC RAM. Updated division of MSMC RAM is shown below: ----------------------------------------- | | | | | U-Boot text |U-Boot | SPL text | | download | Stack | Download + | | | | SPL_BSS + | | | | SPL_STACK | ----------------------------------------- [1] [2] [3] [4] [1] SYS_TEXT_BASE (Start of MSMC RAM) [2] SPL_TEXT_BASE - GBL_DATA_SIZE [3] SPL_TEXT_BASE [4] END of SPL [1] + [2] is at least 1M on all platforms, so no chance of overlap. Reviewed-by: Nishanth Menon Signed-off-by: Lokesh Vutla --- include/configs/ti_armv7_keystone2.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index b441590..58c98ce 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -20,7 +20,7 @@ /* SoC Configuration */ #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_TEXT_BASE 0x0c001000 +#define CONFIG_SYS_TEXT_BASE 0x0c000000 #define CONFIG_SPL_TARGET "u-boot-spi.gph" #define CONFIG_SYS_DCACHE_OFF @@ -29,7 +29,7 @@ #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ GENERATED_GBL_DATA_SIZE) /* SPL SPI Loader Configuration */