From patchwork Thu Aug 13 14:50:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 507044 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3231D14028F for ; Fri, 14 Aug 2015 00:51:31 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4E1A64B778; Thu, 13 Aug 2015 16:51:23 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id O9dF3A81a1nr; Thu, 13 Aug 2015 16:51:23 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0AD6F4B782; Thu, 13 Aug 2015 16:51:22 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8D3694B778 for ; Thu, 13 Aug 2015 16:51:12 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pW8dmECaTHuk for ; Thu, 13 Aug 2015 16:51:12 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 14EAC4B765 for ; Thu, 13 Aug 2015 16:51:07 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t7DEp5CN002044; Thu, 13 Aug 2015 09:51:05 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t7DEp5su011641; Thu, 13 Aug 2015 09:51:05 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Thu, 13 Aug 2015 09:51:05 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t7DEp3Bg031930; Thu, 13 Aug 2015 09:51:03 -0500 From: Nishanth Menon To: Tom Rini , Lokesh Vutla Date: Thu, 13 Aug 2015 09:50:59 -0500 Message-ID: <1439477460-25544-3-git-send-email-nm@ti.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1439477460-25544-1-git-send-email-nm@ti.com> References: <1439477460-25544-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 2/3] ARM: DRA74-evm: Add iodelay values for SR2.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same. Based on data from VayuES2_EVM_Base_Config-20150807. NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification. Signed-off-by: Nishanth Menon Reviewed-by: Tom Rini --- board/ti/dra7xx/evm.c | 36 ++++++++++++++++++++-------- board/ti/dra7xx/mux_data.h | 58 +++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 83 insertions(+), 11 deletions(-) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 94a1a8c25656..9603f10f8ade 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -80,17 +80,33 @@ void set_muxconf_regs_essential(void) #ifdef CONFIG_IODELAY_RECALIBRATION void recalibrate_iodelay(void) { - if (is_dra72x()) { - __recalibrate_iodelay(core_padconf_array_essential, - ARRAY_SIZE(core_padconf_array_essential), - iodelay_cfg_array, - ARRAY_SIZE(iodelay_cfg_array)); - } else { - __recalibrate_iodelay(dra74x_core_padconf_array, - ARRAY_SIZE(dra74x_core_padconf_array), - dra742_iodelay_cfg_array, - ARRAY_SIZE(dra742_iodelay_cfg_array)); + struct pad_conf_entry const *pads; + struct iodelay_cfg_entry const *iodelay; + int npads, niodelays; + + switch (omap_revision()) { + case DRA722_ES1_0: + pads = core_padconf_array_essential; + npads = ARRAY_SIZE(core_padconf_array_essential); + iodelay = iodelay_cfg_array; + niodelays = ARRAY_SIZE(iodelay_cfg_array); + break; + case DRA752_ES1_0: + case DRA752_ES1_1: + pads = dra74x_core_padconf_array; + npads = ARRAY_SIZE(dra74x_core_padconf_array); + iodelay = dra742_es1_1_iodelay_cfg_array; + niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); + break; + default: + case DRA752_ES2_0: + pads = dra74x_core_padconf_array; + npads = ARRAY_SIZE(dra74x_core_padconf_array); + iodelay = dra742_es2_0_iodelay_cfg_array; + niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); + break; } + __recalibrate_iodelay(pads, npads, iodelay, niodelays); } #endif diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index ea8ee9fb3a63..bf401443e465 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -376,7 +376,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { }; #ifdef CONFIG_IODELAY_RECALIBRATION -const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = { +const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = { {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ @@ -431,6 +431,62 @@ const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = { {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ }; + +const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = { + {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 70, 70}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 35, 70}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 100, 130}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 0, 70}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 100, 130}, /* CFG_RGMII0_TXD3_OUT */ + {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */ + {0x08DC, 2105, 619}, /* CFG_VIN1A_D0_IN */ + {0x08E8, 2107, 739}, /* CFG_VIN1A_D10_IN */ + {0x08F4, 2005, 788}, /* CFG_VIN1A_D11_IN */ + {0x0900, 2059, 1297}, /* CFG_VIN1A_D12_IN */ + {0x090C, 2027, 1141}, /* CFG_VIN1A_D13_IN */ + {0x0918, 2071, 1332}, /* CFG_VIN1A_D14_IN */ + {0x0924, 1995, 1764}, /* CFG_VIN1A_D15_IN */ + {0x0930, 1999, 1542}, /* CFG_VIN1A_D16_IN */ + {0x093C, 2072, 1540}, /* CFG_VIN1A_D17_IN */ + {0x0948, 2034, 1629}, /* CFG_VIN1A_D18_IN */ + {0x0954, 2026, 1761}, /* CFG_VIN1A_D19_IN */ + {0x0960, 2017, 757}, /* CFG_VIN1A_D1_IN */ + {0x096C, 2037, 1469}, /* CFG_VIN1A_D20_IN */ + {0x0978, 2077, 1349}, /* CFG_VIN1A_D21_IN */ + {0x0984, 2022, 1545}, /* CFG_VIN1A_D22_IN */ + {0x0990, 2168, 784}, /* CFG_VIN1A_D23_IN */ + {0x099C, 1996, 962}, /* CFG_VIN1A_D2_IN */ + {0x09A8, 1993, 901}, /* CFG_VIN1A_D3_IN */ + {0x09B4, 2098, 499}, /* CFG_VIN1A_D4_IN */ + {0x09C0, 2038, 844}, /* CFG_VIN1A_D5_IN */ + {0x09CC, 2002, 863}, /* CFG_VIN1A_D6_IN */ + {0x09D8, 2063, 873}, /* CFG_VIN1A_D7_IN */ + {0x09E4, 2088, 759}, /* CFG_VIN1A_D8_IN */ + {0x09F0, 2152, 701}, /* CFG_VIN1A_D9_IN */ + {0x09FC, 1926, 728}, /* CFG_VIN1A_DE0_IN */ + {0x0A08, 2043, 937}, /* CFG_VIN1A_FLD0_IN */ + {0x0A14, 1978, 909}, /* CFG_VIN1A_HSYNC0_IN */ + {0x0A20, 1926, 987}, /* CFG_VIN1A_VSYNC0_IN */ + {0x0A70, 140, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 90, 70}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 0, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 0, 70}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */ +}; #endif #endif /* _MUX_DATA_DRA7XX_H_ */