From patchwork Thu Aug 13 03:01:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saket Sinha X-Patchwork-Id: 506831 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 03F471402C3 for ; Thu, 13 Aug 2015 13:01:52 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=MSMziv8R; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C27614B6F3; Thu, 13 Aug 2015 05:01:45 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hFw71Ix3QvQE; Thu, 13 Aug 2015 05:01:45 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D8B6E4B714; Thu, 13 Aug 2015 05:01:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2CC894B70A for ; Thu, 13 Aug 2015 05:01:30 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3T9K3QtuNSw0 for ; Thu, 13 Aug 2015 05:01:30 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f171.google.com (mail-pd0-f171.google.com [209.85.192.171]) by theia.denx.de (Postfix) with ESMTPS id 30E734B6E2 for ; Thu, 13 Aug 2015 05:01:24 +0200 (CEST) Received: by pdrg1 with SMTP id g1so13900878pdr.2 for ; Wed, 12 Aug 2015 20:01:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kP2ZyBQ1mTDfqQMUVBZLxFdnZYCD/l7iLwnIUNhBEyg=; b=MSMziv8RjCG/rIIGvgHZ0ta36R/hEE33jzzyRwZQzCu/q3aEhowlnvDhfKRifwjmDx wJ0v9g1pdm1/ROY+c1nGeh4mP1hDZY/1dxNPHLXYZUpXhDx/Vnx0tC1ZiV3NRpvsufIK diMC7AzA0Yo/X5jsIB9cXd5Y0YtIJj1VCMj1WQVdGmilp/WXKpYv8zab6ecseo0MtDWk DYegryVibAuQWg2e3VHL8LFs/p/YWTV23UAdCMuHycmpayDTD1xcPHJVudkU8VrSBHTN Rq5NW77uL7ecHoZ5vgUHoPiKiGpiGdtxPDUhy1le1dKW0YWxxmg49AwEEjTkI4pPqd1+ yV5A== X-Received: by 10.70.118.71 with SMTP id kk7mr34446445pdb.51.1439434883570; Wed, 12 Aug 2015 20:01:23 -0700 (PDT) Received: from localhost.localdomain ([103.18.72.56]) by smtp.googlemail.com with ESMTPSA id j1sm591984pdn.27.2015.08.12.20.01.21 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 12 Aug 2015 20:01:23 -0700 (PDT) From: Saket Sinha To: u-boot@lists.denx.de Date: Thu, 13 Aug 2015 08:31:02 +0530 Message-Id: <1439434863-18108-4-git-send-email-saket.sinha89@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1439434863-18108-1-git-send-email-saket.sinha89@gmail.com> References: <1439434863-18108-1-git-send-email-saket.sinha89@gmail.com> Cc: sjg@google.com Subject: [U-Boot] [U-BOOT PATCH v3 3/4] x86: Added ACPI support for Qemu. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Saket Sinha --- arch/x86/cpu/qemu/Makefile | 1 + arch/x86/cpu/qemu/acpi.c | 157 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 arch/x86/cpu/qemu/acpi.c diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 9a66b16..8c3884c 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -8,4 +8,5 @@ ifndef CONFIG_EFI_STUB obj-y += car.o dram.o endif obj-y += qemu.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/qemu/acpi.c b/arch/x86/cpu/qemu/acpi.c new file mode 100644 index 0000000..ea2bdc6 --- /dev/null +++ b/arch/x86/cpu/qemu/acpi.c @@ -0,0 +1,157 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase; + + /*TODO get this value from pci rather than harcoding it.*/ + pmbase = 0x0600; + + memset((void *) fadt, 0, sizeof(struct acpi_fadt)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(struct acpi_fadt); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (unsigned long)facs; + fadt->dsdt = (unsigned long)dsdt; + fadt->model = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->sci_int = 0x9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 0x39; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0x00; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 0x06; + fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */ + fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */ + /* then FIRMWARE_CTRL must be zero. */ + + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + fadt->x_pm1b_evt_blk.space_id = 0; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + fadt->x_pm1b_cnt_blk.space_id = 0; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + fadt->x_gpe1_blk.space_id = 0; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + table_compute_checksum((void *)fadt, header->length); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current, 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_irqoverride((struct acpi_madt_irqoverride *)current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((struct acpi_madt_irqoverride *)current, 0, 9, 9, 0xD); + current += acpi_create_madt_irqoverride((struct acpi_madt_irqoverride *)current, 0, 0xB, 0xB, 0xD); + acpi_create_madt_lapic_nmi((struct acpi_madt_lapic_nmi *)current, 0, 0, 0); + + return current; +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((struct acpi_mcfg_mmconfig *)current, + 0xe0000000, 0x0, 0x0, 255); + return current; +}