From patchwork Mon Aug 10 13:05:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 505630 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 927CD14018C for ; Mon, 10 Aug 2015 23:06:32 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=n9BH3o12; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 147FC4BB8A; Mon, 10 Aug 2015 15:06:19 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1-OxDVydrPhQ; Mon, 10 Aug 2015 15:06:18 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C499A4BBB5; Mon, 10 Aug 2015 15:05:54 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 983F44BB7C for ; Mon, 10 Aug 2015 15:05:34 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YNVEFYp3g0Ql for ; Mon, 10 Aug 2015 15:05:34 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-io0-f180.google.com (mail-io0-f180.google.com [209.85.223.180]) by theia.denx.de (Postfix) with ESMTPS id 082A24BB85 for ; Mon, 10 Aug 2015 15:05:28 +0200 (CEST) Received: by iodd187 with SMTP id d187so168224617iod.2 for ; Mon, 10 Aug 2015 06:05:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ejQyITk8h1e0y0/hF2lnIi0WCW4+AYaOEaeLhz+ts68=; b=n9BH3o12pVaUxZYzKWKvPnQnrVI6Lk/mkckwV9zEeLV2XOuiPDls/dLRIIzIJ3x5OK RE06MUqdNLtEt+AH4L2FgO45GZW60gARtVaSN/W8N+8GrpLFhk5XG74uw4+m0sMWss7A 4Prmzaqu/IXAV0dkGx3Qe36SxIci2DhBmFFeiX23JUrqeN/oyJ+i3/NZVN3TNHrINzjC fE0ej5daMMZBFGpcF+IEyQfFCIOHmGHjo4RVwTOPsSM4L9Ad1IWNTaTAnaqATvpGKiRb hKE+6JpMPrZu1D7tdE74ouyk3jzzYOF/qkDVZn+lYw0ex+4YPTQ2nJ5fGrtCLR9pyZg6 bong== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=ejQyITk8h1e0y0/hF2lnIi0WCW4+AYaOEaeLhz+ts68=; b=ketXxWH8AP/pOQ1rI1dLzpabGqbW9NopscnXTEA03YqvUImLbDEogBYntT1axMcqUG merzM3+GqO9iJCYn2hLEyBihw3DnUrlcoZyY+buyWLhZkba2fleZra5r7TdWRhlq7Us7 xoSAQe9jO18NuNQKpayJbC7pH43wfRRmpMKWtNDfsv+3HCpiBxFmwVmUPxwWJBPwEJIh TuroupIVt83YYaaDu7r7mZ4imOC/B/vCg3j6ul9adWltcZ7NgURlvQXHzv1887pT4DLC SLoGeu244tzKZ9sND4ZJIvlIGI/5sK863QUfAsozjp9wuPHMwRiYieiBFN5ZFZza2VHw BOHw== X-Gm-Message-State: ALoCoQmfv1jlxwcO5lL6XHOSYYu9HqB43IW09Y+/RxV5W/Fv7Q++anDCi3QDE6cDe/DgdjXEHl/h X-Received: by 10.107.10.17 with SMTP id u17mr20476490ioi.16.1439211927114; Mon, 10 Aug 2015 06:05:27 -0700 (PDT) Received: from kaki.bld.corp.google.com ([2620:0:1005:1100:3404:902f:f068:b725]) by smtp.gmail.com with ESMTPSA id rq1sm5767983igb.21.2015.08.10.06.05.24 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Aug 2015 06:05:26 -0700 (PDT) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 7A6AB2218DC; Mon, 10 Aug 2015 07:05:23 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Mon, 10 Aug 2015 07:05:09 -0600 Message-Id: <1439211912-10085-8-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.5.0.rc2.392.g76e840b In-Reply-To: <1439211912-10085-1-git-send-email-sjg@chromium.org> References: <1439211912-10085-1-git-send-email-sjg@chromium.org> Cc: Graeme Russ Subject: [U-Boot] [PATCH v3 07/10] x86: minnowmax: Define and enable interrupt setup X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Set up interrupts correctly so that Linux can use all devices. Use savedefconfig to regenerate the defconfig file. Signed-off-by: Simon Glass --- Changes in v3: - Drop unnecessary blank lines - Add PCIe root ports from bayleybay Changes in v2: - Use pirq_init() instead of custom code arch/x86/dts/minnowmax.dts | 59 ++++++++++++++++++++++++++++++++++++++++++--- configs/minnowmax_defconfig | 10 ++++---- include/configs/minnowmax.h | 1 + 3 files changed, 62 insertions(+), 8 deletions(-) diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 9527233..25611bb9 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include /include/ "skeleton.dtsi" /include/ "serial.dtsi" @@ -117,9 +118,61 @@ #address-cells = <3>; #size-cells = <2>; u-boot,dm-pre-reloc; - ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0 0x10000000 - 0x42000000 0x0 0xc0000000 0xc0000000 0 0x10000000 - 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdcb0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0x00, 0x02, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x11, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x12, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x13, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x15, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x18, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x18, 0x02) INTD PIRQD + PCI_BDF(0x00, 0x18, 0x06) INTD PIRQD + PCI_BDF(0x00, 0x18, 0x07) INTB PIRQB + PCI_BDF(0x00, 0x1a, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x1b, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x1c, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x1c, 0x02) INTC PIRQC + PCI_BDF(0x00, 0x1c, 0x03) INTD PIRQD + PCI_BDF(0x00, 0x1d, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x1e, 0x00) INTA PIRQA + PCI_BDF(0x00, 0x1e, 0x01) INTD PIRQD + PCI_BDF(0x00, 0x1e, 0x02) INTB PIRQB + PCI_BDF(0x00, 0x1e, 0x03) INTC PIRQC + PCI_BDF(0x00, 0x1e, 0x04) INTD PIRQD + PCI_BDF(0x00, 0x1e, 0x05) INTB PIRQB + PCI_BDF(0x00, 0x1f, 0x03) INTB PIRQB + + /* PCIe root ports downstream interrupts */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; }; spi { diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index a67597d..9af4aa3 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -5,7 +5,8 @@ CONFIG_TARGET_MINNOWMAX=y CONFIG_HAVE_INTEL_ME=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y -CONFIG_GENERATE_SFI_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set @@ -18,13 +19,12 @@ CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_DM_PCI=y CONFIG_SPI_FLASH=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y -CONFIG_DEBUG_UART=y -CONFIG_DEBUG_UART_NS16550=y -CONFIG_DEBUG_UART_BASE=0x3f8 -CONFIG_DEBUG_UART_CLOCK=1843200 diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 64fa676..aeb04b9 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_ARCH_MISC_INIT #define CONFIG_SMSC_LPC47M