From patchwork Sun Aug 2 23:21:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 502943 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9B0C31402A3 for ; Mon, 3 Aug 2015 09:23:13 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8A6524B95C; Mon, 3 Aug 2015 01:23:04 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 709R50CVLC2B; Mon, 3 Aug 2015 01:23:04 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0C5864B9C0; Mon, 3 Aug 2015 01:22:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8CD844B92F for ; Mon, 3 Aug 2015 01:22:16 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lzyAG6oLx95f for ; Mon, 3 Aug 2015 01:22:16 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by theia.denx.de (Postfix) with ESMTPS id 72EEE4B91D for ; Mon, 3 Aug 2015 01:22:13 +0200 (CEST) Received: from mail.nefkom.net (unknown [192.168.8.184]) by mail-out.m-online.net (Postfix) with ESMTP id 3mkyzm2yTnz3hkdG; Mon, 3 Aug 2015 01:22:12 +0200 (CEST) X-Auth-Info: xC8ilxSW5Tv7OxiGsoKow192cF+/dhtO2NN++rhyrX0= Received: from chi.lan (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3mkyzm0PxQzvdWS; Mon, 3 Aug 2015 01:22:12 +0200 (CEST) From: Marek Vasut To: u-boot@lists.denx.de Date: Mon, 3 Aug 2015 01:21:58 +0200 Message-Id: <1438557722-5254-12-git-send-email-marex@denx.de> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1438557722-5254-1-git-send-email-marex@denx.de> References: <1438557722-5254-1-git-send-email-marex@denx.de> Cc: Marek Vasut Subject: [U-Boot] [PATCH 11/15] ddr: altera: sequencer: Zap VFIFO_SIZE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation. Signed-off-by: Marek Vasut Acked-by: Dinh Nguyen --- drivers/ddr/altera/sequencer.c | 8 ++++---- drivers/ddr/altera/sequencer.h | 3 --- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 70956fa..dd72566 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -1507,7 +1507,7 @@ static void rw_mgr_decr_vfifo(const u32 grp) { u32 i; - for (i = 0; i < VFIFO_SIZE - 1; i++) + for (i = 0; i < READ_VALID_FIFO_SIZE - 1; i++) rw_mgr_incr_vfifo(grp); } @@ -1521,7 +1521,7 @@ static int find_vfifo_failing_read(const u32 grp) { u32 v, ret, fail_cnt = 0; - for (v = 0; v < VFIFO_SIZE; v++) { + for (v = 0; v < READ_VALID_FIFO_SIZE; v++) { debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n", __func__, __LINE__, v); ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, @@ -1592,7 +1592,7 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp, static int sdr_find_phase(int working, const u32 grp, u32 *work, u32 *i, u32 *p) { - const u32 end = VFIFO_SIZE + (working ? 0 : 1); + const u32 end = READ_VALID_FIFO_SIZE + (working ? 0 : 1); int ret; for (; *i < end; (*i)++) { @@ -1773,7 +1773,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn, * push vfifo until we can successfully calibrate. We can do this * because the largest possible margin in 1 VFIFO cycle. */ - for (i = 0; i < VFIFO_SIZE; i++) { + for (i = 0; i < READ_VALID_FIFO_SIZE; i++) { debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n"); if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index 3f6f7b6..a80f227 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -65,9 +65,6 @@ #define CAL_SUBSTAGE_READ_LATENCY 1 #define CAL_SUBSTAGE_REFRESH 1 -/* length of VFIFO, from SW_MACROS */ -#define VFIFO_SIZE (READ_VALID_FIFO_SIZE) - #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200