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[U-Boot,V2,2/3] ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration

Message ID 1438032367-26214-3-git-send-email-nm@ti.com
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

Nishanth Menon July 27, 2015, 9:26 p.m. UTC 
Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/cpu/armv7/omap5/hwinit.c           | 6 ++++++
 arch/arm/include/asm/arch-omap5/sys_proto.h | 1 +
 2 files changed, 7 insertions(+)

Comments

Tom Rini Aug. 13, 2015, 1:20 p.m. UTC | #1 
On Mon, Jul 27, 2015 at 04:26:06PM -0500, Nishanth Menon wrote:

> Implement logic for ACR(Auxiliary Control Register) configuration using
> ROM Code smc service.
> 
> Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
> Suggested-by: Brad Griffis <bgriffis@ti.com>
> Reviewed-by: Brad Griffis <bgriffis@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>

Applied to u-boot/master, thanks!
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Patch

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 39f8d0d5e200..bc19aebc6db7 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -418,3 +418,9 @@  void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 {
 	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
 }
+
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+			  u32 cpu_variant, u32 cpu_rev)
+{
+	omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
+}
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 6da8297c7292..7fcb78389403 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -81,5 +81,6 @@  static inline u32 usec_to_32k(u32 usec)
 }
 
 #define OMAP5_SERVICE_L2ACTLR_SET    0x104
+#define OMAP5_SERVICE_ACR_SET        0x107
 
 #endif