From patchwork Mon Jul 27 20:52:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 500801 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B509C1402B7 for ; Tue, 28 Jul 2015 07:13:49 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DFFA04B785; Mon, 27 Jul 2015 23:07:24 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Cn9AgJRk9bmS; Mon, 27 Jul 2015 23:07:24 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6F2F64BE34; Mon, 27 Jul 2015 23:04:53 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8EBA94B78D for ; Mon, 27 Jul 2015 22:54:45 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fsMxcD3elm3J for ; Mon, 27 Jul 2015 22:54:45 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9]) by theia.denx.de (Postfix) with ESMTPS id 5A7894B717 for ; Mon, 27 Jul 2015 22:54:05 +0200 (CEST) Received: from mail.nefkom.net (unknown [192.168.8.184]) by mail-out.m-online.net (Postfix) with ESMTP id 3mgCzd0sRgz3hjZC; Mon, 27 Jul 2015 22:54:05 +0200 (CEST) X-Auth-Info: 5TJ+3VWEGCWh3CVSwz/KNWcWeJjPVaWt9Vlwpcq6ndY= Received: from chi.lan (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3mgCzc60lYzvdWS; Mon, 27 Jul 2015 22:54:04 +0200 (CEST) From: Marek Vasut To: u-boot@lists.denx.de Date: Mon, 27 Jul 2015 22:52:08 +0200 Message-Id: <1438030335-10631-166-git-send-email-marex@denx.de> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1438030335-10631-1-git-send-email-marex@denx.de> References: <1438030335-10631-1-git-send-email-marex@denx.de> Cc: Marek Vasut , trini@konsulko.com Subject: [U-Boot] [PATCH 165/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This function is implementing the DDR calibration Stage 3 as described in Altera EMI_RM 2015.05.04 . The main body of this function is almost identical to Stage 1.3 (DQ/DQS centering) for all but two flags -- use_read_test and update_fom. Convert this function to call rw_mgr_mem_calibrate_dq_dqs_centering() with the correct flags set to trim down the code duplication. Moreover, reorder the remnants in the function a little and convert the function to return either 0 or -EIO in case of success and failure respectively, to match the common return value convention. Signed-off-by: Marek Vasut --- drivers/ddr/altera/sequencer.c | 59 +++++++++++++++--------------------------- 1 file changed, 21 insertions(+), 38 deletions(-) diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 6ae8a65..2baf77d 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -2788,51 +2788,34 @@ cal_done_ok: return 1; } -/* VFIFO Calibration -- Read Deskew Calibration after write deskew */ -static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group, - uint32_t test_bgn) +/** + * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering. + * @rw_group: Read/Write Group + * @test_bgn: Rank at which the test begins + * + * Stage 3: DQ/DQS Centering. + * + * This function implements UniPHY calibration Stage 3, as explained in + * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". + */ +static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group, + const u32 test_bgn) { - uint32_t rank_bgn, sr; - uint32_t grp_calibrated; - uint32_t write_group; - - debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn); + int ret; - /* update info for sims */ + debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn); + /* Update info for sims. */ + reg_file_set_group(rw_group); reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES); reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); - write_group = read_group; - - /* update info for sims */ - reg_file_set_group(read_group); - - grp_calibrated = 1; - /* Read per-bit deskew can be done on a per shadow register basis */ - for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS; - rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) { - /* Determine if this set of ranks should be skipped entirely */ - if (!param->skip_shadow_regs[sr]) { - /* This is the last calibration round, update FOM here */ - if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn, - read_group, - test_bgn, 0, - 1)) { - grp_calibrated = 0; - } - } - } - - - if (grp_calibrated == 0) { - set_failing_group_stage(write_group, + ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1); + if (ret) + set_failing_group_stage(rw_group, CAL_STAGE_VFIFO_AFTER_WRITES, CAL_SUBSTAGE_VFIFO_CENTER); - return 0; - } - - return 1; + return ret; } /* Calibrate LFIFO to find smallest read latency */ @@ -3483,7 +3466,7 @@ static uint32_t mem_calibrate(void) if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) continue; - if (rw_mgr_mem_calibrate_vfifo_end(read_group, + if (!rw_mgr_mem_calibrate_vfifo_end(read_group, read_test_bgn)) continue;