[U-Boot] ARM: OMAP5/DRA7: Provide workaround for ARM erratum 801819

ARM erratum 801819 ("An eviction from L1 data cache might stall
indefinitely in the L2 write buffer preventing a snoop from
completing") applies to A15 which may not have the erratum fix
integrated (CPUID maynot exactly help here, since certain SoC
versions might choose to pick up just the fix and no update in MIDR
register.

OMAP5 and DRA7 family of processors (at least the current revisions) do
not have the fix integrated.

Errata summary is that "A livelock can occur in the L2 cache arbitration
that might prevent a snoop from completing. Under certain conditions
this can cause the system to deadlock. "

Recommended workaround is as follows:
Do both of the following:

1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.

For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:

3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111

So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk. Most TI platforms used for development
may probably never see it, so, this is not enabled by default.

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/cpu/armv7/omap5/Kconfig  |  7 +++++++
 arch/arm/cpu/armv7/omap5/hwinit.c | 11 +++++++++++
 2 files changed, 18 insertions(+)

On 07/24/2015 10:12 AM, Nishanth Menon wrote:
> ARM erratum 801819 ("An eviction from L1 data cache might stall
> indefinitely in the L2 write buffer preventing a snoop from
> completing") applies to A15 which may not have the erratum fix
> integrated (CPUID maynot exactly help here, since certain SoC
> versions might choose to pick up just the fix and no update in MIDR
> register.
> 
> OMAP5 and DRA7 family of processors (at least the current revisions) do
> not have the fix integrated.
> 
> Errata summary is that "A livelock can occur in the L2 cache arbitration
> that might prevent a snoop from completing. Under certain conditions
> this can cause the system to deadlock. "
> 
> Recommended workaround is as follows:
> Do both of the following:
> 
> 1) Do not use the write-back no-allocate memory type.
> 2) Do not issue write-back cacheable stores at any time when the cache
> is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
> is implementation defined whether cacheable stores update the cache when
> the cache is disabled it is not expected that any portable code will
> execute cacheable stores when the cache is disabled.
> 
> For implementations of Cortex-A15 configured without the “L2 arbitration
> register slice” option (typically one or two core systems), you must
> also do the following:
> 
> 3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
> 
> So, we provide an option to disable write streaming on OMAP5 and DRA7.
> It is a rare condition to occur and may be enabled selectively based
> on platform acceptance of risk. Most TI platforms used for development
> may probably never see it, so, this is not enabled by default.
> 
> Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
> Suggested-by: Brad Griffis <bgriffis@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm/cpu/armv7/omap5/Kconfig  |  7 +++++++
>  arch/arm/cpu/armv7/omap5/hwinit.c | 11 +++++++++++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
> index 20c3bd963bc6..6a85848f229e 100644
> --- a/arch/arm/cpu/armv7/omap5/Kconfig
> +++ b/arch/arm/cpu/armv7/omap5/Kconfig
> @@ -21,6 +21,13 @@ endchoice
>  config SYS_SOC
>  	default "omap5"
>  
> +config TI_ARM_ERRATA_801819
> +	bool "Enable erratum workaround for 801819"
> +	help
> +	  Disable streaming as a workaround for ARM erratum 801819
> +	  NOTE: Enabling this erratum workaround may have severe
> +	  performance issues for a potentially rare deadlock condition
> +
>  source "board/compulab/cm_t54/Kconfig"
>  source "board/ti/omap5_uevm/Kconfig"
>  source "board/ti/dra7xx/Kconfig"
> diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
> index 39f8d0d5e200..0d57d78f6e4f 100644
> --- a/arch/arm/cpu/armv7/omap5/hwinit.c
> +++ b/arch/arm/cpu/armv7/omap5/hwinit.c
> @@ -330,6 +330,17 @@ void init_cpu_configuration(void)
>  	 * 8: Disable DVM/CMO message broadcast
>  	 */
>  	l2actlr |= 0x118;
> +
> +#ifdef CONFIG_TI_ARM_ERRATA_801819
> +	/*
> +	 * 28:27 Disables streaming. All write-allocate lines allocate in the L1
> +	 * or L2 cache
> +	 * 26:25 - Disables streaming. All write-allocate lines allocate in
> +	 * the L1 cache.
> +	 */
> +	l2actlr |= (0x3 << 27) | (0x3 << 25);
> +#endif
> +
>  	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
>  }
>  
> 

Sorry about that.. I was supposed to write to ACTLR register, not
L2ACTLR register.. NAK for my own patch. :(