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[U-Boot,v3,3/7] ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE

Message ID 1437589418-11978-4-git-send-email-alexanders83@web.de
State Superseded
Delegated to: Tom Rini
Headers show

Commit Message

Alexander Stein July 22, 2015, 6:23 p.m. UTC 
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.

Signed-off-by: Alexander Stein <alexanders83@web.de>
---
 include/configs/rpi-common.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Stephen Warren July 24, 2015, 4:54 a.m. UTC | #1 
On 07/22/2015 12:23 PM, Alexander Stein wrote:
> The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
> config level for cache handling code.

>  include/configs/rpi-common.h | 1 +

This file applies to both RPi 1 and RPi 2. Do they have the same
cacheline size?
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Patch

diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index 1012cdd..e75fb1e 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -15,6 +15,7 @@ 
 #define CONFIG_BCM2835
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE		32
 
 #define CONFIG_SYS_TIMER_RATE		1000000
 #define CONFIG_SYS_TIMER_COUNTER	\