From patchwork Wed Jul 22 08:21:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 498439 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EC2BD1402C6 for ; Wed, 22 Jul 2015 18:20:19 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=nthj7d2K; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 369B24B69E; Wed, 22 Jul 2015 10:19:59 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fdZ6oy6aWikZ; Wed, 22 Jul 2015 10:19:59 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 22EE54B6C3; Wed, 22 Jul 2015 10:19:48 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 26FAB4B656 for ; Wed, 22 Jul 2015 10:19:25 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9TYLxNXfB3tp for ; Wed, 22 Jul 2015 10:19:25 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f48.google.com (mail-pa0-f48.google.com [209.85.220.48]) by theia.denx.de (Postfix) with ESMTPS id 8A5D44B657 for ; Wed, 22 Jul 2015 10:19:13 +0200 (CEST) Received: by pabkd10 with SMTP id kd10so62739030pab.2 for ; Wed, 22 Jul 2015 01:19:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=DwKtWcNFmW7/pkCkhjG5cCiTbM8TzQ3xPARIW/cWzH4=; b=nthj7d2KbBLuJMTE9JjL75Cq7iAJsUFp81Lb/uRVZCHD0c1BMthhstMoCXGOGqCDgC REmn7MoPD5f+HDcq7Inn21X0TYOFSW7uKZXDpLNZ4znSsogf43LZia8nF4qqPYWaidzy BVCjc6rcUMmjvNfpqQhJhIaITu1zCLNGEEBqZJMwXIWYBqUHAn/xfqyjff0HSVczRMqS QwNmFPciauDIsv7YaQKI32XAhMylUdDl0+NStJ4cbu4c8JvpCJu2UFx+2tYi7ul/JPcn t+8t1/61gn23FUZnyZcsprfD60WakEum9edgBuieIeRWswLhsZ47gLo0RAmJOCIE9v5g Oi6g== X-Received: by 10.70.89.199 with SMTP id bq7mr3262662pdb.168.1437553152478; Wed, 22 Jul 2015 01:19:12 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id q5sm1709699pde.56.2015.07.22.01.19.11 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Jul 2015 01:19:11 -0700 (PDT) From: Bin Meng To: Simon Glass , U-Boot Mailing List , Saket Sinha Date: Wed, 22 Jul 2015 01:21:15 -0700 Message-Id: <1437553275-30727-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1437553275-30727-1-git-send-email-bmeng.cn@gmail.com> References: <1437553275-30727-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 7/7] x86: Reserve PCIe ECAM address range in the E820 table X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We should mark PCIe ECAM address range in the E820 table as reserved otherwise kernel will not attempt to use ECAM. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v3: None Changes in v2: - New patch to reserve PCIe ECAM address range in the E820 table arch/x86/Kconfig | 10 ++++++++++ arch/x86/lib/fsp/fsp_dram.c | 6 ++++++ arch/x86/lib/zimage.c | 5 ++++- 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cbbaa4f..e8968a7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -369,4 +369,14 @@ config PCIE_ECAM_BASE assigned to PCI devices - i.e. the memory and prefetch regions, as passed to pci_set_region(). +config PCIE_ECAM_SIZE + hex + default 0x10000000 + help + This is the size of memory-mapped address of PCI configuration space, + which is only available through the Enhanced Configuration Access + Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, + so a default 0x10000000 size covers all of the 256 buses which is the + maximum number of PCI buses as defined by the PCI specification. + endmenu diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 4c0a7c8..28552fa 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -77,5 +77,11 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) num_entries++; } + /* Mark PCIe ECAM address range as reserved */ + entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; + entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; + entries[num_entries].type = E820_RESERVED; + num_entries++; + return num_entries; } diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 144471c..a1ec57e 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -61,8 +61,11 @@ __weak unsigned install_e820_map(unsigned max_entries, entries[2].addr = ISA_END_ADDRESS; entries[2].size = gd->ram_size - ISA_END_ADDRESS; entries[2].type = E820_RAM; + entries[3].addr = CONFIG_PCIE_ECAM_BASE; + entries[3].size = CONFIG_PCIE_ECAM_SIZE; + entries[3].type = E820_RESERVED; - return 3; + return 4; } static void build_command_line(char *command_line, int auto_boot)