From patchwork Wed Jul 22 08:21:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 498438 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 40FEA1402C6 for ; Wed, 22 Jul 2015 18:20:11 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=hfC5WMIb; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E7B004B6CD; Wed, 22 Jul 2015 10:19:54 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PPbyV0iygh9K; Wed, 22 Jul 2015 10:19:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 295354B6D5; Wed, 22 Jul 2015 10:19:46 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E2A7A4B699 for ; Wed, 22 Jul 2015 10:19:24 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NbflXwoVeCUl for ; Wed, 22 Jul 2015 10:19:24 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f182.google.com (mail-pd0-f182.google.com [209.85.192.182]) by theia.denx.de (Postfix) with ESMTPS id 7EF5F4B656 for ; Wed, 22 Jul 2015 10:19:12 +0200 (CEST) Received: by pdbnt7 with SMTP id nt7so64088088pdb.0 for ; Wed, 22 Jul 2015 01:19:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=td7EMR/ZtYItO2nNrPUggy3NpanDJlwKpYZIm7HGs7M=; b=hfC5WMIbypMwxXAv0+GMM1Vh9iUMZPc7391hWvI2UzGclmUcbvCqzPswH9YHo6s0gP /7aR1CaVQfFkgsxPYFz2Tasi1uXLF/s4ONYmoUwkSxSHdHI/kYzF8y0lpMFyPyrgG+PO x0+aNOGo18U5DLUqGOhZFs+czQyjqe7zYulij8enqyuq1G0Y3bMwS1xDjuHjObTpZQh5 6dM39TlDScmFmifA2nNOAwTqgeD8MHPwv8lgBmSZgSsCleyR0KsZsFjO/RazRUfPtWd/ ZPwrO9TD6NF5Bqrb4Ib0chiCGhxfkbnqCigg5VVyppAsLVenP9n1SA5FrJhgA8pfgbXY kpyA== X-Received: by 10.70.37.144 with SMTP id y16mr3404323pdj.86.1437553151209; Wed, 22 Jul 2015 01:19:11 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id q5sm1709699pde.56.2015.07.22.01.19.10 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Jul 2015 01:19:10 -0700 (PDT) From: Bin Meng To: Simon Glass , U-Boot Mailing List , Saket Sinha Date: Wed, 22 Jul 2015 01:21:14 -0700 Message-Id: <1437553275-30727-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1437553275-30727-1-git-send-email-bmeng.cn@gmail.com> References: <1437553275-30727-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 6/7] x86: qemu: Turn on PCIe ECAM address range decoding on Q35 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Turn on PCIe ECAM address range decoding on Q35. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v3: None Changes in v2: None arch/x86/cpu/qemu/pci.c | 4 ++++ arch/x86/include/asm/arch-qemu/qemu.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index acbd922..2e94456 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -90,6 +90,10 @@ int board_pci_post_scan(struct pci_controller *hose) xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); xbcs |= APIC_EN; x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); + } else { + /* Configure PCIe ECAM base address */ + x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, + CONFIG_PCIE_ECAM_BASE | BAR_EN); } /* diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h index 8c8e4ac..b67d342 100644 --- a/arch/x86/include/asm/arch-qemu/qemu.h +++ b/arch/x86/include/asm/arch-qemu/qemu.h @@ -22,6 +22,10 @@ #define IDE1_TIM 0x42 #define IDE_DECODE_EN (1 << 15) +/* PCIe ECAM Base Address Register */ +#define PCIEX_BAR 0x60 +#define BAR_EN (1 << 0) + /* I/O Ports */ #define CMOS_ADDR_PORT 0x70 #define CMOS_DATA_PORT 0x71