From patchwork Thu Jul 16 02:27:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas MANOCHA X-Patchwork-Id: 496531 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A549D1402B1 for ; Thu, 16 Jul 2015 12:36:04 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EB8BA4B6D5; Thu, 16 Jul 2015 04:35:45 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KO6uW0ptZN4O; Thu, 16 Jul 2015 04:35:45 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3ABD64B6B4; Thu, 16 Jul 2015 04:35:33 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 976AF4B62B for ; Thu, 16 Jul 2015 04:35:28 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id r7BB3ZNU9gkE for ; Thu, 16 Jul 2015 04:35:28 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by theia.denx.de (Postfix) with ESMTPS id 047354B67B for ; Thu, 16 Jul 2015 04:35:14 +0200 (CEST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id t6G2XTJF018969; Thu, 16 Jul 2015 04:35:13 +0200 Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx08-00178001.pphosted.com with ESMTP id 1vnt5wt65j-1 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 16 Jul 2015 04:35:13 +0200 Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 1E79323; Thu, 16 Jul 2015 02:35:09 +0000 (GMT) Received: from Webmail-ap.st.com (eapex1hubcas2.st.com [10.80.176.10]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id B4EC492D; Thu, 16 Jul 2015 02:35:07 +0000 (GMT) Received: from localhost (10.41.34.229) by Webmail-ap.st.com (10.80.176.7) with Microsoft SMTP Server (TLS) id 8.3.342.0; Thu, 16 Jul 2015 10:35:06 +0800 From: Vikas Manocha To: , , , Date: Wed, 15 Jul 2015 19:27:34 -0700 Message-ID: <1437013654-29387-7-git-send-email-vikas.manocha@st.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1437013654-29387-1-git-send-email-vikas.manocha@st.com> References: <1437013654-29387-1-git-send-email-vikas.manocha@st.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.14.151, 1.0.33, 0.0.0000 definitions=2015-07-15_07:2015-07-15, 2015-07-15, 1970-01-01 signatures=0 Subject: [U-Boot] [v2 6/6] spi: cadence_qspi: get fifo width from device tree X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Fifo width could be different on different socs, e.g. stv0991 & altera soc have different fifo width. Signed-off-by: Vikas Manocha --- Changes in v2: Rebased to master arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/stv0991.dts | 1 + drivers/spi/cadence_qspi.c | 1 + drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 13 ++++--------- 5 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 1099a92..ee43762 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -640,6 +640,7 @@ ext-decoder = <0>; /* external decoder */ num-cs = <4>; fifo-depth = <128>; + fifo-width = <4>; sram-size = <128>; bus-num = <2>; status = "disabled"; diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index e23d4fd..f0f450b 100644 --- a/arch/arm/dts/stv0991.dts +++ b/arch/arm/dts/stv0991.dts @@ -34,6 +34,7 @@ <0x40000000 0x0000010>; clocks = <3750000>; sram-size = <256>; + fifo-width = <8>; status = "okay"; flash0: n25q32@0 { diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 95c9cea..bfcd39e 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -311,6 +311,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); + plat->fifo_width = fdtdec_get_int(blob, node, "fifo-width", 4); debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \ page-size=%d\n", __func__, plat->regbase, plat->flashbase, diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 7341339..91f38f1 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -27,6 +27,7 @@ struct cadence_spi_platdata { u32 tchsh_ns; u32 tslch_ns; u32 sram_size; + u32 fifo_width; }; struct cadence_spi_priv { diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e11f715..e5da225 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -34,8 +34,6 @@ #define CQSPI_REG_RETRY (10000) #define CQSPI_POLL_IDLE_RETRY (3) -#define CQSPI_FIFO_WIDTH (4) - #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) /* Transfer mode */ @@ -48,9 +46,6 @@ #define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4) - -#define CQSPI_REG_SRAM_FILL_THRESHOLD \ - ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) /**************************************************************************** * Controller's configuration and status register (offset from QSPI_BASE) ****************************************************************************/ @@ -230,11 +225,11 @@ static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat, page_size : remaining; remaining -= wr_bytes; - while (wr_bytes >= CQSPI_FIFO_WIDTH) { - for (i = 0; i < CQSPI_FIFO_WIDTH/sizeof(dest_addr); i++) + while (wr_bytes >= plat->fifo_width) { + for (i = 0; i < plat->fifo_width/sizeof(dest_addr); i++) writel(*(src_ptr+i), dest_addr+i); - src_ptr += CQSPI_FIFO_WIDTH/sizeof(dest_addr); - wr_bytes -= CQSPI_FIFO_WIDTH; + src_ptr += plat->fifo_width/sizeof(dest_addr); + wr_bytes -= plat->fifo_width; } if (wr_bytes) { /* dangling bytes */