From patchwork Wed Jul 15 12:03:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Schubert X-Patchwork-Id: 495803 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 526FA1402AE for ; Wed, 15 Jul 2015 22:04:52 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Gc8ykfK1; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B5E514B691; Wed, 15 Jul 2015 14:04:49 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id M_d9xak4yGK3; Wed, 15 Jul 2015 14:04:49 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 33BC54B676; Wed, 15 Jul 2015 14:04:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4B9154B676 for ; Wed, 15 Jul 2015 14:04:45 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hVoHPGiOloWQ for ; Wed, 15 Jul 2015 14:04:45 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f169.google.com (mail-wi0-f169.google.com [209.85.212.169]) by theia.denx.de (Postfix) with ESMTPS id 146F54B669 for ; Wed, 15 Jul 2015 14:04:41 +0200 (CEST) Received: by widjy10 with SMTP id jy10so126934706wid.1 for ; Wed, 15 Jul 2015 05:04:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=fyTg1IWmhEdh15JlxHTO/g7yDZ3GW9LEJeZ5vdRDOPE=; b=Gc8ykfK1jAXUZfegK6u31OypZL64NQEN6FyW2jUNxyswhe8CqF58IHqt9vKO06+kxF ykY/E7v2M2GTL39z6e8GFNsLnnTtXAtr9EgkKUX6R1s7mX1gqm4RkflztrQUy/sIIX4T nudoXcK8yw+vfUzG+UE0Cw+Dgu+W7dxn2XwQarKTF26F13xwISuzXEzQzyyKbVH7eTaz GNUdIR1i8oYSL8Nlw+rep/79Q4DWBXVXZFj+XxT2HB+6ynwopLnElcjr3NaMvSBimYvx AMfbTybYLjIHpIKnocIQf8HUfG5PkN0qfr2OxMYE1c4N+WPI5YJSJed8fOrL+d8lRDGK ixiA== X-Received: by 10.180.20.15 with SMTP id j15mr15593087wie.76.1436961880955; Wed, 15 Jul 2015 05:04:40 -0700 (PDT) Received: from localhost.localdomain ([176.2.111.24]) by smtp.gmail.com with ESMTPSA id ck18sm7564446wjb.47.2015.07.15.05.04.39 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Jul 2015 05:04:40 -0700 (PDT) From: Anton Schubert To: u-boot@lists.denx.de Date: Wed, 15 Jul 2015 14:03:46 +0200 Message-Id: <1436961826-12461-1-git-send-email-anton.schubert@gmx.de> X-Mailer: git-send-email 2.3.6 Cc: Stefan Roese , Luka Perkov Subject: [U-Boot] [PATCH v2] add Armada XP SATA support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch initializes the SATA address windows on Armada XP and allows it to work with the existing mvsata_ide driver. It also adds the necessary configuration for the db-mv784mp-gp board. Changes v2: - add second bus offset - only allow one device per bus - enable CONFIG_CMD_IDE per default Signed-off-by: Anton Schubert Cc: Stefan Roese Cc: Luka Perkov Tested-by: Stefan Roese --- arch/arm/mach-mvebu/include/mach/soc.h | 1 + drivers/block/mvsata_ide.c | 41 ++++++++++++++++++++++++++++++++++ include/configs/db-mv784mp-gp.h | 29 ++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 1aaea67..619bc7e 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -52,6 +52,7 @@ #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) #define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) +#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index e54d564..52c1602 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -13,6 +13,8 @@ #include #elif defined(CONFIG_KIRKWOOD) #include +#elif defined(CONFIG_ARMADA_XP) +#include #endif /* SATA port registers */ @@ -90,6 +92,41 @@ struct mvsata_port_registers { #define MVSATA_STATUS_TIMEOUT -1 /* + * Registers for SATA MBUS memory windows + */ + +#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4)) +#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4)) + +/* + * Initialize SATA memory windows for Armada XP + */ + +#ifdef CONFIG_ARMADA_XP +static void mvsata_ide_conf_mbus_windows(void) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + /* Disable windows, Set Size/Base to 0 */ + for (i = 0; i < 4; i++) { + writel(0, MVSATA_WIN_CONTROL(i)); + writel(0, MVSATA_WIN_BASE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + MVSATA_WIN_CONTROL(i)); + writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i)); + } +} +#endif + +/* * Initialize one MVSATAHC port: set SControl's IPM to "always active" * and DET to "reset", then wait for SStatus's DET to become "device and * comm ok" (or time out after 50 us if no device), then set SControl's @@ -137,6 +174,10 @@ int ide_preinit(void) int ret = MVSATA_STATUS_TIMEOUT; int status; +#ifdef CONFIG_ARMADA_XP + mvsata_ide_conf_mbus_windows(); +#endif + /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) status = mvsata_ide_initialize_port( diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index c33a588..0fdf3a5 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -32,6 +32,7 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_TFTPPUT #define CONFIG_CMD_TIME +#define CONFIG_CMD_IDE /* I2C */ #define CONFIG_SYS_I2C @@ -60,6 +61,34 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ #define CONFIG_SYS_ALT_MEMTEST +/* SATA support */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_MVSATA_IDE + +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO + +#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for normal register accesses*/ +#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 + +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 + +/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS + +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000 + +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_CMD_IDE */ + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros