From patchwork Thu Jul 2 11:03:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 490579 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6CE521402BA for ; Thu, 2 Jul 2015 21:05:04 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 310AD4B6F3; Thu, 2 Jul 2015 13:05:01 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xsb5M4xg6QtU; Thu, 2 Jul 2015 13:05:00 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 60EE34B69C; Thu, 2 Jul 2015 13:04:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1E9B64B689 for ; Thu, 2 Jul 2015 13:04:16 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id T6mcL4HQf293 for ; Thu, 2 Jul 2015 13:04:16 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-by2-obe.outbound.protection.outlook.com (mail-by2on0137.outbound.protection.outlook.com [207.46.100.137]) by theia.denx.de (Postfix) with ESMTPS id 3276B4B664 for ; Thu, 2 Jul 2015 13:04:04 +0200 (CEST) Received: from CY1PR0301MB0684.namprd03.prod.outlook.com (10.160.158.155) by CY1PR0301MB1593.namprd03.prod.outlook.com (10.162.166.19) with Microsoft SMTP Server (TLS) id 15.1.207.12; Thu, 2 Jul 2015 11:04:00 +0000 Received: from CO2PR03CA0030.namprd03.prod.outlook.com (10.141.194.157) by CY1PR0301MB0684.namprd03.prod.outlook.com (10.160.158.155) with Microsoft SMTP Server (TLS) id 15.1.201.16; Thu, 2 Jul 2015 11:03:59 +0000 Received: from BY2FFO11OLC013.protection.gbl (2a01:111:f400:7c0c::152) by CO2PR03CA0030.outlook.office365.com (2a01:111:e400:1414::29) with Microsoft SMTP Server (TLS) id 15.1.201.16 via Frontend Transport; Thu, 2 Jul 2015 11:03:59 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11OLC013.mail.protection.outlook.com (10.1.15.25) with Microsoft SMTP Server (TLS) id 15.1.201.10 via Frontend Transport; Thu, 2 Jul 2015 11:03:59 +0000 Received: from linux-jyl1.ap.freescale.net (b51431-11.ap.freescale.net [10.193.102.175]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t62B3Dq7001943; Thu, 2 Jul 2015 04:03:56 -0700 From: Peng Fan To: Date: Thu, 2 Jul 2015 19:03:00 +0800 Message-ID: <1435834988-13032-4-git-send-email-Peng.Fan@freescale.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1435834988-13032-1-git-send-email-Peng.Fan@freescale.com> References: <1435834988-13032-1-git-send-email-Peng.Fan@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11OLC013; 1:QHRU8KxEbx6+x6+siutvlShwIXk0XtF8Qs4CKgyLMAWwcZ0ZnvLd0MU2vt4JHEYzITiEbm+smWXJeMmJ3fRp0HtAZZP2flXRU1Dfyb/5W02dEhePubdiU++N33H8ygwNGLe62QN8kYqs0JDVYhJjKOJl5uV3MrGET7Y57ApvDiQKWP1PzUjj7Zkc2GsIU95X8eEG2qtxVnpxHN3bGRxa2rCxWq3rKj7YGlaWofgDAvGsHeMFSrkb5qL3q6ISO0khv+6trSFaN85Gh/NbXIFn1XeIPLJYgHgzow533xAoK6Bsw3NXRraBNUNLg2IJK3yzCd6FbX/+SK2Wh8ok71i8cg== X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(2980300002)(339900001)(189002)(199003)(46102003)(189998001)(110136002)(107886002)(5001960100002)(86362001)(36756003)(575784001)(77096005)(50986999)(76176999)(2950100001)(92566002)(47776003)(48376002)(50226001)(50466002)(19580395003)(19580405001)(6806004)(87936001)(77156002)(62966003)(105606002)(106466001)(104016003)(85426001)(229853001)(2351001)(32563001)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR0301MB0684; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:; MIME-Version: 1.0 X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0684; 2:+FuXJVTymLq3eMwI1QOM7yZxLvysJwYeAzcEXDzgVbVD7wjthSNXuX3BcqRPs0tK; 3:uKznwuMLke35dmb7i1nKh25jswp1C4xE1ls05eT5ccyNg4BxBEFbx4oN0sefj/TCV5/lXWwuJ1yAl1wNsTnbQQ+TRR5NJ8Txi6dlonngGni0XqSX99FBZOkvqbLAoeJIHC6kTPkFTKmoKJZkmwv+oxnGfGsE37iPsfhFv8k7u9a5lzXRSF9GNffP49cJ+h6dSM+CIKwaiSXqk4XyOHi0Vkzylub7pfF7k3npmZHkq6A=; 25:rGCDUXOu3Q9wpq2cGZFJuZWe3vKeZxtxgd0AmBsrCOK79lZxbXPHcgk0Wc3rhh40xlVrQC70oe5n4DnN7mLbT+rflzNJ4mPjgSV+mB7Wha7bzW26gGg41Fa3G/WhBmTjix3Lr44VaMg2B0jBHLr9pE3GhqknIlzO1yfmcdcybnSNL64Z8IwxHCKbjVk/+7egSatJWfDNic9vMlKgTesjiYSjGsz+7g/Cl8M1UQc5/oZ5QQWSdpCyVINOv4bD0hk+jlgmT54ZyWp+ShcGGVnACQ==; 20:lrhFKCYN8XDuFYbQmIXmsnL+Wa7ZwYWhF/6HUf0sjdZbyUi0X/J4PytO8m3xgDJH+cFQ4+ohjOFiWBw+JBnnOZVSwzgvn2z8rjz/Ahlrb+b7Z+oGB57Sz3avrb8LTBiLwDHi/GqWO02SRF43GjaywcvVReHyP3bqtw1Sj/8lu54lGx7HCg/hBya0gHt/v/8GTG1JcoWu6wZLqRqIluEdYIqJO60f8CYT/bqX7pdSsoDSf6A+NZ8S5xzALGMnJKtT9CL5wGQRTyDdx6rDeuhMiD0HJNCM5qbd2kZbGeQOZDUV+2++Ct61UtljlwRebB1E1pykYAfFi1MK0pyIJzzbwh3LowRB0zw/SPLcW/s3WVU= X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0301MB0684; UriScan:; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0301MB1593; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:CY1PR0301MB0684; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0301MB0684; X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0684; 4:gOiqHkjrUlRswwDv2WVcnt8KthZLGjb35Ex44pMZJmGNLyKApmWO7jfFyaYkRsE3TY/dFGBXpL2IQM1rxkRx9TJvGnWDNRivx1mqMBzdFABqB7K80b3vFOW8q6L160YAdpk0LJgPh6hiRuKBeMOZQ2M31f9YxLtO7diYZ5oSVP8WPUeMH4DMCU8f1oMiZRQS8asg1JbTBI28o7oClZAOcNmwoQqM/pehgts7qnhN4gVwpe1AwI0IyrKFENNvqk4IhBcl24UpxaQvgNbtfJlnV5RDVmEQXkNzIlW3s6bAsTE= X-Forefront-PRVS: 06259BA5A2 X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0684; 23:fLeZw5f3IFT6HSM6xJ8Ls4brTDaudH9/Oeig2UI/gwq8EyEhEl1LH8gf+y3OZeV+/inXl01ATDT4LTRwlKH4TF3Zj+Y29UJialOJHvNkv9WYbrBQVn+jCVyBry7UqI/q7p6fOdt8RwUZgwGQ39n6iCcZGVMCZk/BxalLcRIYNPiAKug6ZwFOZBh92k/ePgaMNs0v6URv3bplV/gdcNsyta8oiHUSfkNyLLa+xE5Py/IWI7LmBGjvKZxzX5aknO0XS7ozWwJRslNUuNn6nPukf8PpXTPDfaE6rqDBNxgScAAUiIQ1P0UqyjMoEOVsVmhVhc4zwtNsfYlNSlMV1NfIbohsUaXUstC98eSbndaApkhTQ+UQWfhWPtMrXee625r3HqrWGLxuchX/u9C7P+vkIway+UYpeGuxmQj/VeKYGZEc4mH4W8LAL5+zkMM2cqJ4iwqdMhPiP4zzsKDYX9qQWb/TJphtdLptHzufV/sEr8gTghwqfwZ2jtB9UvlPawQlkQoNYiFOpbBcN6nn3Xfr+33VCLRHCGtZsM8k7MpBWdLv6xIp19CWDp7q47nLyGfus3l+gkYcl6ngJmrYOL4W7iOulPhoIAgj+jEA+GxIrL8K0UsTjnpLIR+Szqnprt03FUHQSzW3vpx8xgDGyJnGs/LxDx9tDGdkw4UXK4fC/FuOLvVWM+pm3VIAIYxdV1Ms/CYTACafNqHmHLej+YCT+nr/8jzlEsc0ddkYQbOzncivFy6krh+AuNhERyqFXWo+G6O/7r828v66Re9Ixq20PwO6GZ+RjnqVI3oz+UbBHjVHyrMu1ufP8mKVgu1xq5Km2iPZXJkmBQMOz4uClLc0LuDZQYw9CnYHTysl0ffNPDQLhA66To0G17XJKfWM1rrFtuy707RFw4PTOWjiGr1DyEM55TpcESIxmN89N/Cc8k5Ua4ZOVspYcWNdOMYQASUN X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0684; 5:L8vVv7BIrgfBnhJug2OHmWFoUUNgm1dr2hktsoXKnsOUyBSZHPjOh1x1/N2M/ZsGLe3z3fxVVgFDayaHK5hKIo74Xgbow0p5YY9d6rMfcG/2kWl3QkHKSIMl+0GyszZ1XJWOzqFC2//sY05K5sqO6g==; 24:pTIJJDBlHqgRudSKy27BvSURD9LuMn/I3zSS2kJOCqANw/B1P4lwYDfvxhSpXYKufSqOeXvhqsX90cz/suABmdECCCDRv383QXt+Ij93MUI=; 20:wvaTVQ2REfsWmCo+y3oGz61x16KsmO0GjYMODKXr/KSYrVBPGXMjLPEeHN0V0DfKdGvTZ1e1HQkk3W2KjViObw== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2015 11:03:59.1398 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB0684 X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1593; 2:AEUhlULn8kz8ueECWZE3IznP16abkSJJigSyQFCrcOmU1pm5wjQTWhENxg1VeNDg; 3:XtrSlmst3F7359iars7LzGmCqJ9E+COKz5J+bQ1+O7YvJgYLeeNrAzfe9+DMqqEI2z1R/V41pNmPegtrEJp/ArJZHx2OXxBfJ7gnZuXMyEb+n+WiWBw+Hufd7AthLT2/r50Xuc0ZQ8TClMQRrz1zM0juS84IO0RGA5FEQcJulfRB8OSvSA2R5lqCxTr88sbjjtYG6He1HZ3+UfchMsgfdeWqdpnw39oaW8wNndbObWM=; 25:WuKAXPTKxnBnDopFsY/rDyp4qexUCzQEtU/P0dr1Pn5RkLmsjsUK5PMkVEavFwvUGsxKrMUKCIFKe5/t8FFQX6eT6192mH5OUJCj3g6LEScPzPX9sQ+WkZYVflQuufW3pe5Jm9ttsM2RSX9Uyj6HQ6rYnef016dkczV4gw4ZJwlVZoGxAp3AXuHfTv3tTGbncgTksEhRRyUhwaafa6lsGDox8ucbnpayCvwswzC/dkDT7zKgdm/jrfYxFUuuN28bwkuFDG8yus3YRxF9exT3aA==; 23:kNEH8+LYpx7oOVEOYw4vvAGjDRaMBdsu13dUrYztE5JurRNfnIXPZvuJHOZbDcoNKdoSDvv8YBAkRO8hPAyJO1rKI9JlOo1cw9Urlfm/PBKZYAAEn/+eFMqutLh9L58/ljgLGRkKxnT4CoDcX76tRo5hqvWAIUZ3BAPSQ1cdu2esvhC1Ynxu6LNX4X1+5cYyKQaYMyHSrMMiaAloc6z1nYXDiBFlb7Tlt80E+5toTTkzSh9stgFzQVpF01ffHiAg X-OriginatorOrg: freescale.com Cc: fabio.estevam@freescale.com, marex@denx.de, otavio@ossystems.com.br, u-boot@lists.denx.de Subject: [U-Boot] [PATCH 03/11] imx: mx6ul: Update imx registers head file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Update imx register base address for i.MX6UL Signed-off-by: Peng Fan Signed-off-by: Ye.Li --- arch/arm/include/asm/arch-mx6/imx-regs.h | 60 ++++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 19 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 35a324c..d78daac 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -9,7 +9,11 @@ #define ARCH_MXC +#ifdef CONFIG_MX6UL +#define CONFIG_SYS_CACHELINE_SIZE 64 +#else #define CONFIG_SYS_CACHELINE_SIZE 32 +#endif #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x000FFFFF @@ -19,7 +23,7 @@ #define GPU_2D_ARB_END_ADDR 0x02203FFF #define OPENVG_ARB_BASE_ADDR 0x02204000 #define OPENVG_ARB_END_ADDR 0x02207FFF -#elif CONFIG_MX6SX +#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_END_ADDR 0x00107FFF #define GPU_ARB_BASE_ADDR 0x01800000 @@ -28,10 +32,6 @@ #define APBH_DMA_ARB_END_ADDR 0x0180BFFF #define M4_BOOTROM_BASE_ADDR 0x007F8000 -#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR -#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) -#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) - #else #define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_END_ADDR 0x00103FFF @@ -52,13 +52,13 @@ #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) /* GPV - PL301 configuration ports */ -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #define GPV2_BASE_ADDR 0x00D00000 #else #define GPV2_BASE_ADDR 0x00200000 #endif -#ifdef CONFIG_MX6SX +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #define GPV3_BASE_ADDR 0x00E00000 #define GPV4_BASE_ADDR 0x00F00000 #define GPV5_BASE_ADDR 0x01000000 @@ -96,6 +96,11 @@ #define QSPI0_AMBA_END 0x6FFFFFFF #define QSPI1_AMBA_BASE 0x70000000 #define QSPI1_AMBA_END 0x7FFFFFFF +#elif defined(CONFIG_MX6UL) +#define WEIM_ARB_BASE_ADDR 0x50000000 +#define WEIM_ARB_END_ADDR 0x57FFFFFF +#define QSPI0_AMBA_BASE 0x60000000 +#define QSPI0_AMBA_END 0x6FFFFFFF #else #define SATA_ARB_BASE_ADDR 0x02200000 #define SATA_ARB_END_ADDR 0x02203FFF @@ -111,7 +116,7 @@ #define WEIM_ARB_END_ADDR 0x0FFFFFFF #endif -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #define MMDC0_ARB_BASE_ADDR 0x80000000 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF #define MMDC1_ARB_BASE_ADDR 0xC0000000 @@ -179,8 +184,13 @@ #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) +#ifdef CONFIG_MX6UL +#define SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#else #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#endif #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) @@ -249,6 +259,12 @@ #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) +#ifdef CONFIG_MX6UL +#define CSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) +#define LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#define LCDIF2_BASE_ADDR LCDIF1_BASE_ADDR +#define PXP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) +#else #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #ifdef CONFIG_MX6SX @@ -256,19 +272,23 @@ #else #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) #endif +#endif #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#ifdef CONFIG_MX6SX +#ifdef CONFIG_MX6UL +#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) +#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) +#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR +#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#elif defined(CONFIG_MX6SX) #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) -#else -#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) -#endif #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) -#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) -#ifdef CONFIG_MX6SX #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) #else +#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) @@ -313,7 +333,7 @@ #define CHIP_REV_1_2 0x12 #define CHIP_REV_1_5 0x15 #define CHIP_REV_2_0 0x20 -#ifndef CONFIG_MX6SX +#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #define IRAM_SIZE 0x00040000 #else #define IRAM_SIZE 0x00020000 @@ -451,7 +471,7 @@ struct src { struct iomuxc { -#ifdef CONFIG_MX6SX +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) u8 reserved[0x4000]; #endif u32 gpr[14]; @@ -577,7 +597,7 @@ struct cspi_regs { #define MXC_CSPICON_POL 4 /* SCLK polarity */ #define MXC_CSPICON_SSPOL 12 /* SS polarity */ #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ -#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) +#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ ECSPI2_BASE_ADDR, \ @@ -661,7 +681,7 @@ struct fuse_bank1_regs { u32 rsvd7[3]; }; -#ifdef CONFIG_MX6SX +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) struct fuse_bank4_regs { u32 sjc_resp_low; u32 rsvd0[3]; @@ -674,7 +694,9 @@ struct fuse_bank4_regs { u32 mac_addr2; u32 rsvd4[7]; u32 gp1; - u32 rsvd5[7]; + u32 rsvd5[3]; + u32 gp2; + u32 rsvd6[3]; }; #else struct fuse_bank4_regs {