From patchwork Tue Jun 23 23:28:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 487862 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 32FE7140316 for ; Wed, 24 Jun 2015 09:30:59 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=MlYNS5mF; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 273EE4B6F5; Wed, 24 Jun 2015 01:30:43 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HAYaHA6FzzT3; Wed, 24 Jun 2015 01:30:43 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0BDE54B691; Wed, 24 Jun 2015 01:30:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6BB104B686 for ; Wed, 24 Jun 2015 01:29:55 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YUNdE8ot2-up for ; Wed, 24 Jun 2015 01:29:55 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ig0-f175.google.com (mail-ig0-f175.google.com [209.85.213.175]) by theia.denx.de (Postfix) with ESMTPS id 516FB4B663 for ; Wed, 24 Jun 2015 01:29:49 +0200 (CEST) Received: by igin14 with SMTP id n14so22957829igi.1 for ; Tue, 23 Jun 2015 16:29:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=kblom1wfEjw0C9AGrs75GtmdyNLCN/a/c9+zMN6/7WM=; b=MlYNS5mF1PiNpcPAMegy6gatr5Z2D8bO0FLxXrJ/y9Y0bFt6uvv9Z1nGya1e6Pr4fL cs6yDVh9lIFDKPMzp8XtRWfJwzBIA4T2A8i7Z2xT1ZZDhmwuGaWoZVIiWBqANE9o5dQO EMVpcFBP0y4CZG6rvaEm91GE0OmcMZ9NiWgaSufSuJvGi/GJgQEOqwpAC72wCrurhCUw jiRJwzx2jA6IR59EGUVC8OrTTsQG/Rf2sbjUdxd1wRCziQhv0uGRFgo2mti7VSLfr1og Mk9mcjEDuLCTcobnMdFOJRg7sUaIZztoyoPnV5eBkg4ExnTYdP7VfA3IEO3F9P8cnJj+ 1PdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=kblom1wfEjw0C9AGrs75GtmdyNLCN/a/c9+zMN6/7WM=; b=Wy/lkIPekvhs5jUwBU8mKJt8BytivXzdzsBeYUp0AvSqq76yWlBEAtY0991+xfNPLa hO/q4BdU8uJDPA2pFngXgr/7UM78BREo5eIn8yVnDrp3keRoYIgDavV0G6X16VazhzEu LoZ4mp9Vs4hbB72uyRMOjoduVA7ZSa2OdQ44/Ak+W5BB7WTmtI6M5EHbC8TRM1A3ii7S xX7UIe0KCWxNnHTkOYDhYD6P9hOMdWfUfaMfBJfuUOnXTqesCXexg+JQ3VJViLyeuTaj C2T5q6LdwDFjG0vi9+AxnBk/hAEN2RxzgfIrCBCbjsd3MQ63qlH/FDRwOddePIrueJt4 Bw4A== X-Gm-Message-State: ALoCoQmyRsNuBOmIV1O1Lvb8+aFsMgGWSvWw4wmGQV5w3/hJJbTT7BwOYK4/frU9iuUd2uXR3DoF X-Received: by 10.42.167.129 with SMTP id s1mr35385697icy.54.1435102188215; Tue, 23 Jun 2015 16:29:48 -0700 (PDT) Received: from kaki.bld.corp.google.com ([2620:0:1005:1100:29dc:b646:97d0:4c6e]) by mx.google.com with ESMTPSA id b15sm787612igm.12.2015.06.23.16.29.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Jun 2015 16:29:46 -0700 (PDT) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 494CE2210FF; Tue, 23 Jun 2015 17:29:43 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Tue, 23 Jun 2015 17:28:54 -0600 Message-Id: <1435102150-29438-10-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.4.3.573.g4eafbef In-Reply-To: <1435102150-29438-1-git-send-email-sjg@chromium.org> References: <1435102150-29438-1-git-send-email-sjg@chromium.org> Cc: huangtao , Tom Rini , Tom Cubie , cwx Subject: [U-Boot] [PATCH v3 09/25] rockchip: gpio: Add rockchip GPIO driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This supports RK3288 at present. It does not implement functions or support for pull up/down. Signed-off-by: Simon Glass --- Changes in v3: None Changes in v2: None arch/arm/include/asm/arch-rockchip/gpio.h | 28 +++++++ drivers/gpio/Kconfig | 9 +++ drivers/gpio/Makefile | 1 + drivers/gpio/rk_gpio.c | 123 ++++++++++++++++++++++++++++++ 4 files changed, 161 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h create mode 100644 drivers/gpio/rk_gpio.c diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h new file mode 100644 index 0000000..e39218d --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/gpio.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_GPIO_H +#define _ASM_ARCH_GPIO_H + +struct rockchip_gpio_regs { + u32 swport_dr; + u32 swport_ddr; + u32 reserved0[(0x30 - 0x08) / 4]; + u32 inten; + u32 intmask; + u32 inttype_level; + u32 int_polarity; + u32 int_status; + u32 int_rawstatus; + u32 debounce; + u32 porta_eoi; + u32 ext_port; + u32 reserved1[(0x60 - 0x54) / 4]; + u32 ls_sync; +}; +check_member(rockchip_gpio_regs, ls_sync, 0x60); + +#endif diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 0c43777..8f5d3e7 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -15,6 +15,15 @@ config LPC32XX_GPIO help Support for the LPC32XX GPIO driver. +config ROCKCHIP_GPIO + bool "Rockchip GPIO driver" + depends on DM_GPIO + help + Support GPIO access on Rockchip SoCs. The GPIOs are arranged into + a number of banks (different for each SoC type) each with 32 GPIOs. + The GPIOs for a device are defined in the device tree with one node + for each bank. + config SANDBOX_GPIO bool "Enable sandbox GPIO driver" depends on SANDBOX && DM && DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 67c6374..bdd2d7e 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_PCA953X) += pca953x.o obj-$(CONFIG_PCA9698) += pca9698.o +obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o obj-$(CONFIG_S5P) += s5p_gpio.o obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c new file mode 100644 index 0000000..fbdf9f3 --- /dev/null +++ b/drivers/gpio/rk_gpio.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * (C) Copyright 2008-2014 Rockchip Electronics + * Peter, Software Engineering, . + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +enum { + ROCKCHIP_GPIOS_PER_BANK = 32, +}; + +#define OFFSET_TO_BIT(bit) (1UL << (bit)) + +struct rockchip_gpio_priv { + struct rockchip_gpio_regs *regs; + char name[2]; +}; + +static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct rockchip_gpio_priv *priv = dev_get_priv(dev); + struct rockchip_gpio_regs *regs = priv->regs; + + clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset)); + + return 0; +} + +static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + struct rockchip_gpio_priv *priv = dev_get_priv(dev); + struct rockchip_gpio_regs *regs = priv->regs; + int mask = OFFSET_TO_BIT(offset); + + clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0); + setbits_le32(®s->swport_ddr, mask); + + return 0; +} + +static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct rockchip_gpio_priv *priv = dev_get_priv(dev); + struct rockchip_gpio_regs *regs = priv->regs; + + return readl(®s->ext_port) & OFFSET_TO_BIT(offset); +} + +static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct rockchip_gpio_priv *priv = dev_get_priv(dev); + struct rockchip_gpio_regs *regs = priv->regs; + int mask = OFFSET_TO_BIT(offset); + + clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0); + + return 0; +} + +static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) +{ + return -ENOSYS; +} + +static int rockchip_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args) +{ + desc->offset = args->args[0]; + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + + return 0; +} + +static int rockchip_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct rockchip_gpio_priv *priv = dev_get_priv(dev); + char *end; + int bank; + + priv->regs = (struct rockchip_gpio_regs *)dev_get_addr(dev); + uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK; + end = strrchr(dev->name, '@'); + bank = trailing_strtoln(dev->name, end); + priv->name[0] = 'A' + bank; + uc_priv->bank_name = priv->name; + + return 0; +} + +static const struct dm_gpio_ops gpio_rockchip_ops = { + .direction_input = rockchip_gpio_direction_input, + .direction_output = rockchip_gpio_direction_output, + .get_value = rockchip_gpio_get_value, + .set_value = rockchip_gpio_set_value, + .get_function = rockchip_gpio_get_function, + .xlate = rockchip_gpio_xlate, +}; + +static const struct udevice_id rockchip_gpio_ids[] = { + { .compatible = "rockchip,gpio-bank" }, + { } +}; + +U_BOOT_DRIVER(gpio_rockchip) = { + .name = "gpio_rockchip", + .id = UCLASS_GPIO, + .of_match = rockchip_gpio_ids, + .ops = &gpio_rockchip_ops, + .priv_auto_alloc_size = sizeof(struct rockchip_gpio_priv), + .probe = rockchip_gpio_probe, +};