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[U-Boot,1/4] config: lsch3: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A

Message ID 1435032921-24049-1-git-send-email-nikhil.badola@freescale.com
State Superseded
Delegated to: York Sun
Headers show

Commit Message

Nikhil Badola June 23, 2015, 4:15 a.m. UTC
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
---
This patchset depends on a patchset sent to u-boot-usb/next
http://patchwork.ozlabs.org/patch/487462/

 arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index ca8d38c..02332dc 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -10,6 +10,7 @@ 
 #include <fsl_ddrc_version.h>
 
 #define CONFIG_SYS_PAGE_SIZE		0x10000
+#define CONFIG_SYS_CACHELINE_SIZE	64
 
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT		6