| Message ID | 1433688642-19861-9-git-send-email-sjg@chromium.org |
|---|---|
| State | Superseded |
| Delegated to: | Simon Glass |
| Headers | show |
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass <sjg@chromium.org> wrote: > Adjust minnowmax to use driver model for PCI. This requires adding a device > tree node to specify the ranges, removing the board-specific PCI code and > ensuring that the host bridge is configured. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > arch/x86/cpu/baytrail/Makefile | 1 - > arch/x86/cpu/baytrail/pci.c | 46 ------------------------------------------ > arch/x86/dts/minnowmax.dts | 10 +++++++++ > configs/minnowmax_defconfig | 1 + > include/configs/minnowmax.h | 1 + > 5 files changed, 12 insertions(+), 47 deletions(-) > delete mode 100644 arch/x86/cpu/baytrail/pci.c > > diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile > index c78b644..5be5491 100644 > --- a/arch/x86/cpu/baytrail/Makefile > +++ b/arch/x86/cpu/baytrail/Makefile > @@ -7,5 +7,4 @@ > obj-y += cpu.o > obj-y += early_uart.o > obj-y += fsp_configs.o > -obj-y += pci.o > obj-y += valleyview.o > diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c > deleted file mode 100644 > index 48409de..0000000 > --- a/arch/x86/cpu/baytrail/pci.c > +++ /dev/null > @@ -1,46 +0,0 @@ > -/* > - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> > - * > - * SPDX-License-Identifier: GPL-2.0+ > - */ > - > -#include <common.h> > -#include <pci.h> > -#include <asm/pci.h> > -#include <asm/fsp/fsp_support.h> > - > -DECLARE_GLOBAL_DATA_PTR; > - > -void board_pci_setup_hose(struct pci_controller *hose) > -{ > - hose->first_busno = 0; > - hose->last_busno = 0; > - > - /* PCI memory space */ > - pci_set_region(hose->regions + 0, > - CONFIG_PCI_MEM_BUS, > - CONFIG_PCI_MEM_PHYS, > - CONFIG_PCI_MEM_SIZE, > - PCI_REGION_MEM); > - > - /* PCI IO space */ > - pci_set_region(hose->regions + 1, > - CONFIG_PCI_IO_BUS, > - CONFIG_PCI_IO_PHYS, > - CONFIG_PCI_IO_SIZE, > - PCI_REGION_IO); > - > - pci_set_region(hose->regions + 2, > - CONFIG_PCI_PREF_BUS, > - CONFIG_PCI_PREF_PHYS, > - CONFIG_PCI_PREF_SIZE, > - PCI_REGION_PREFETCH); > - > - pci_set_region(hose->regions + 3, > - 0, > - 0, > - gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000, > - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); > - > - hose->region_count = 4; > -} > diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts > index bd21bfb..0e59b18 100644 > --- a/arch/x86/dts/minnowmax.dts > +++ b/arch/x86/dts/minnowmax.dts > @@ -111,6 +111,16 @@ > > }; > > + pci { > + compatible = "intel,pci-baytrail", "pci-x86"; > + #address-cells = <3>; > + #size-cells = <2>; > + u-boot,dm-pre-reloc; > + ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0 0x10000000 > + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x10000000 > + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; > + }; > + > spi { > #address-cells = <1>; > #size-cells = <0>; > diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig > index 744aca3..ff2bfda 100644 > --- a/configs/minnowmax_defconfig > +++ b/configs/minnowmax_defconfig > @@ -12,3 +12,4 @@ CONFIG_CMD_CPU=y > CONFIG_CMD_NET=y > CONFIG_OF_CONTROL=y > CONFIG_CPU=y > +CONFIG_DM_PCI=y > diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h > index d4d28a7..41653ba 100644 > --- a/include/configs/minnowmax.h > +++ b/include/configs/minnowmax.h > @@ -32,6 +32,7 @@ > #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS > #define CONFIG_PCI_IO_SIZE 0xe000 > > +#define CONFIG_PCI_CONFIG_HOST_BRIDGE > #define CONFIG_SYS_EARLY_PCI_INIT > #define CONFIG_PCI_PNP > #define CONFIG_RTL8169 > -- Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile index c78b644..5be5491 100644 --- a/arch/x86/cpu/baytrail/Makefile +++ b/arch/x86/cpu/baytrail/Makefile @@ -7,5 +7,4 @@ obj-y += cpu.o obj-y += early_uart.o obj-y += fsp_configs.o -obj-y += pci.o obj-y += valleyview.o diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c deleted file mode 100644 index 48409de..0000000 --- a/arch/x86/cpu/baytrail/pci.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <pci.h> -#include <asm/pci.h> -#include <asm/fsp/fsp_support.h> - -DECLARE_GLOBAL_DATA_PTR; - -void board_pci_setup_hose(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_PREF_BUS, - CONFIG_PCI_PREF_PHYS, - CONFIG_PCI_PREF_SIZE, - PCI_REGION_PREFETCH); - - pci_set_region(hose->regions + 3, - 0, - 0, - gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; -} diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index bd21bfb..0e59b18 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -111,6 +111,16 @@ }; + pci { + compatible = "intel,pci-baytrail", "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 744aca3..ff2bfda 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -12,3 +12,4 @@ CONFIG_CMD_CPU=y CONFIG_CMD_NET=y CONFIG_OF_CONTROL=y CONFIG_CPU=y +CONFIG_DM_PCI=y diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index d4d28a7..41653ba 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -32,6 +32,7 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0xe000 +#define CONFIG_PCI_CONFIG_HOST_BRIDGE #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_RTL8169
Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Signed-off-by: Simon Glass <sjg@chromium.org> --- arch/x86/cpu/baytrail/Makefile | 1 - arch/x86/cpu/baytrail/pci.c | 46 ------------------------------------------ arch/x86/dts/minnowmax.dts | 10 +++++++++ configs/minnowmax_defconfig | 1 + include/configs/minnowmax.h | 1 + 5 files changed, 12 insertions(+), 47 deletions(-) delete mode 100644 arch/x86/cpu/baytrail/pci.c