From patchwork Fri Jun 5 20:39:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 481553 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2C638140134 for ; Sat, 6 Jun 2015 06:46:37 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=dNeefGyN; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 208B54B6CD; Fri, 5 Jun 2015 22:46:30 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MPVj9x9-PB7t; Fri, 5 Jun 2015 22:46:30 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3EBDD4B6B4; Fri, 5 Jun 2015 22:46:08 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B81BB4B65A for ; Fri, 5 Jun 2015 22:45:54 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id q7eK8cQwOwxW for ; Fri, 5 Jun 2015 22:45:54 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ie0-f174.google.com (mail-ie0-f174.google.com [209.85.223.174]) by theia.denx.de (Postfix) with ESMTPS id 4EECB4B660 for ; Fri, 5 Jun 2015 22:45:50 +0200 (CEST) Received: by iesa3 with SMTP id a3so65889852ies.2 for ; Fri, 05 Jun 2015 13:45:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=j+05ipJDj1qFRqsK10M7lutmh+m08FQzWtvZ4oWIlKo=; b=dNeefGyNZ5DfMVg15B9eDb0uwd25GmY+J88c4x4PLbqoGgdxfE1bv+5eQvpzVa29rn gN86IraSku2n+IOteANBP3la9bAuhJf5h/+gJwQ4/Pw7LUDKB2EbHR+MFOfXRezqbH2/ YC+YjLONkLLw3qRTQrJR4woTo+rfqld+HxR7uyboPntqrCllrP9rObP1vhORosiT/WlE +cYPNzEF1jqb/K4tCmvLOS89CxGDV53gDQu8cG9Xn6VMgt0Xzea5TVRa2kSVY2juhp16 8TjRIs+UdEr9Fdt/8oP2Ek9uEWcR5a9JJB74ezSGQ7qmgo+KoFs0W0mhSXeehDxAhFn8 Q7gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=j+05ipJDj1qFRqsK10M7lutmh+m08FQzWtvZ4oWIlKo=; b=io4jQrda9BlBBJ/aXf6zXAm96NAErCtgzO/dE9tB/jJdsRn1xaaxHYKt5h+KXsQjod 7BLJkhDmoAP3K/VM2OvLavpdTWB6Y+gV1bsGdHPZ98yZqAnLE55DpgtbkG7DXA7BcSL3 qfUwRZSrQ65SsKoX6X+nz49gDicfE8ZwrcXEJD9qHOWnYJX2cRvBdFndeCeW5VkqwycZ eUxykl++T8xkeexm6dOskEtTpuoFFz53/5YbR5ugsjDXk6EtO1r88vxIAJOZcKbuifFR XJC/DYt5YCA8qaIVtVHrKBH2xUrSD5knLkoaTyYtROxPVdXbJVToi0VEfzSpmi/MvM6p d93Q== X-Gm-Message-State: ALoCoQkMmY1WRBGJvhjYd75eclfvYdxzE4d0EyVskAzSa5Voy/J3QulE5KHv9cqhELV6uqqhYDmC X-Received: by 10.107.18.92 with SMTP id a89mr5392642ioj.14.1433537149154; Fri, 05 Jun 2015 13:45:49 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by mx.google.com with ESMTPSA id s5sm2041967igh.6.2015.06.05.13.45.46 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Jun 2015 13:45:47 -0700 (PDT) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id A9B06221554; Fri, 5 Jun 2015 14:39:51 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Fri, 5 Jun 2015 14:39:38 -0600 Message-Id: <1433536786-11857-8-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1433536786-11857-2-git-send-email-sjg@chromium.org> References: <1433536786-11857-2-git-send-email-sjg@chromium.org> Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH v3 07/15] tegra: Introduce SRAM repair on tegra124 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is required in order to avoid instability when running from caches after the kernel starts. Signed-off-by: Simon Glass --- Changes in v3: None Changes in v2: None arch/arm/include/asm/arch-tegra124/flow.h | 12 ++++++++++++ arch/arm/mach-tegra/powergate.c | 20 +++++++++++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h index d6f515f..7818b1b 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -26,6 +26,12 @@ struct flow_ctlr { u32 cpu_pwr_csr; /* offset 0x38 */ u32 mpid; /* offset 0x3c */ u32 ram_repair; /* offset 0x40 */ + u32 flow_dbg_sel; /* offset 0x44 */ + u32 flow_dbg_cnt0; /* offset 0x48 */ + u32 flow_dbg_cnt1; /* offset 0x4c */ + u32 flow_dbg_qual; /* offset 0x50 */ + u32 flow_ctlr_spare; /* offset 0x54 */ + u32 ram_repair_cluster1;/* offset 0x58 */ }; /* HALT_COP_EVENTS_0, 0x04 */ @@ -43,4 +49,10 @@ struct flow_ctlr { #define CSR_WAIT_WFI_SHIFT 8 #define CSR_PWR_OFF_STS (1 << 16) +/* RAM_REPAIR, 0x40, 0x58 */ +enum { + RAM_REPAIR_REQ = 0x1 << 0, + RAM_REPAIR_STS = 0x1 << 1, +}; + #endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 6331cd4..30ae036 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -9,7 +9,7 @@ #include #include - +#include #include #include @@ -75,11 +75,29 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id) return 0; } +static void tegra_powergate_ram_repair(void) +{ +#ifdef CONFIG_TEGRA124 + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; + + /* Request RAM repair for cluster 0 and wait until complete */ + setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); + while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS)) + ; + + /* Same for cluster 1 */ + setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); + while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS)) + ; +#endif +} + int tegra_powergate_sequence_power_up(enum tegra_powergate id, enum periph_id periph) { int err; + tegra_powergate_ram_repair(); reset_set_enable(periph, 1); err = tegra_powergate_power_on(id);