diff mbox

[U-Boot,RFC,08/11] mtd/nand: Add DT definitions for Olimex Lime

Message ID 1433505164-24112-9-git-send-email-r.spliet@ultimaker.com
State RFC
Delegated to: Scott Wood
Headers show

Commit Message

Roy Spliet June 5, 2015, 11:52 a.m. UTC 
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
---
 arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 41 ++++++++++++++
 arch/arm/dts/sun7i-a20.dtsi               | 90 +++++++++++++++++++++++++++++++
 2 files changed, 131 insertions(+)

Comments

Boris Brezillon June 14, 2015, 11:39 a.m. UTC | #1 
On Fri,  5 Jun 2015 13:52:41 +0200
Roy Spliet <r.spliet@ultimaker.com> wrote:

> Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
> ---
>  arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 41 ++++++++++++++
>  arch/arm/dts/sun7i-a20.dtsi               | 90 +++++++++++++++++++++++++++++++
>  2 files changed, 131 insertions(+)
> 
> diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
> index 6592cb2..cc5e65d 100644
> --- a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
> +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
> @@ -181,3 +181,44 @@
>  	usb2_vbus-supply = <&reg_usb2_vbus>;
>  	status = "okay";
>  };
> +
> +&nfc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
> +	status = "okay";
> +
> +	nand@0 {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		reg = <0>;
> +		allwinner,rb = <0>;
> +		nand-ecc-mode = "hw";
> +		nand-ecc-strength = <40>;
> +		nand-ecc-step-size = <1024>;
> +		nand-rnd-mode = "hw";
> +		nand-randomizer-seeds = /bits/ 16 <
> +			0x2b75 0x0bd0 0x5ca3 0x62d1 0x1c93 0x07e9 0x2162 0x3a72
> +			0x0d67 0x67f9 0x1be7 0x077d 0x032f 0x0dac 0x2716 0x2436
> +			0x7922 0x1510 0x3860 0x5287 0x480f 0x4252 0x1789 0x5a2d
> +			0x2a49 0x5e10 0x437f 0x4b4e 0x2f45 0x216e 0x5cb7 0x7130
> +			0x2a3f 0x60e4 0x4dc9 0x0ef0 0x0f52 0x1bb9 0x6211 0x7a56
> +			0x226d 0x4ea7 0x6f36 0x3692 0x38bf 0x0c62 0x05eb 0x4c55
> +			0x60f4 0x728c 0x3b6f 0x2037 0x7f69 0x0936 0x651a 0x4ceb
> +			0x6218 0x79f3 0x383f 0x18d9 0x4f05 0x5c82 0x2912 0x6f17
> +			0x6856 0x5938 0x1007 0x61ab 0x3e7f 0x57c2 0x542f 0x4f62
> +			0x7454 0x2eac 0x7739 0x42d4 0x2f90 0x435a 0x2e52 0x2064
> +			0x637c 0x66ad 0x2c90 0x0bad 0x759c 0x0029 0x0986 0x7126
> +			0x1ca7 0x1605 0x386a 0x27f5 0x1380 0x6d75 0x24c3 0x0f8e
> +			0x2b7a 0x1418 0x1fd1 0x7dc1 0x2d8e 0x43af 0x2267 0x7da3
> +			0x4e3d 0x1338 0x50db 0x454d 0x764d 0x40a3 0x42e6 0x262b
> +			0x2d2e 0x1aea 0x2e17 0x173d 0x3a6e 0x71bf 0x25f9 0x0a5d
> +			0x7c57 0x0fbe 0x46ce 0x4939 0x6b17 0x37bb 0x3e91 0x76db>;
> +		onfi,nand-timing-mode = <0x1f>;

Can we use the same binding we have in mainline Linux (not my branch).
In mainline, the onfi,nand-timing-mode has been dropped in favor of
ONFI timing mode definition in the nand_ids table.
ECC strength and step size should also be extracted from the nand_ids
table, unless you want to force something different (which doesn't seem
to be the case here).
Moreover, the randomizer stuff haven't been reviewed/accepted yet.
To support the randomizer stuff in the meantime, you could define the
randomizer-seeds table in the board config header and use sunxi
specific commands to select the randomizer mode and randomizer seeds
table (if you have several tables).
diff mbox

Patch

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
index 6592cb2..cc5e65d 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
@@ -181,3 +181,44 @@ 
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";
 };
+
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+	status = "okay";
+
+	nand@0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0>;
+		allwinner,rb = <0>;
+		nand-ecc-mode = "hw";
+		nand-ecc-strength = <40>;
+		nand-ecc-step-size = <1024>;
+		nand-rnd-mode = "hw";
+		nand-randomizer-seeds = /bits/ 16 <
+			0x2b75 0x0bd0 0x5ca3 0x62d1 0x1c93 0x07e9 0x2162 0x3a72
+			0x0d67 0x67f9 0x1be7 0x077d 0x032f 0x0dac 0x2716 0x2436
+			0x7922 0x1510 0x3860 0x5287 0x480f 0x4252 0x1789 0x5a2d
+			0x2a49 0x5e10 0x437f 0x4b4e 0x2f45 0x216e 0x5cb7 0x7130
+			0x2a3f 0x60e4 0x4dc9 0x0ef0 0x0f52 0x1bb9 0x6211 0x7a56
+			0x226d 0x4ea7 0x6f36 0x3692 0x38bf 0x0c62 0x05eb 0x4c55
+			0x60f4 0x728c 0x3b6f 0x2037 0x7f69 0x0936 0x651a 0x4ceb
+			0x6218 0x79f3 0x383f 0x18d9 0x4f05 0x5c82 0x2912 0x6f17
+			0x6856 0x5938 0x1007 0x61ab 0x3e7f 0x57c2 0x542f 0x4f62
+			0x7454 0x2eac 0x7739 0x42d4 0x2f90 0x435a 0x2e52 0x2064
+			0x637c 0x66ad 0x2c90 0x0bad 0x759c 0x0029 0x0986 0x7126
+			0x1ca7 0x1605 0x386a 0x27f5 0x1380 0x6d75 0x24c3 0x0f8e
+			0x2b7a 0x1418 0x1fd1 0x7dc1 0x2d8e 0x43af 0x2267 0x7da3
+			0x4e3d 0x1338 0x50db 0x454d 0x764d 0x40a3 0x42e6 0x262b
+			0x2d2e 0x1aea 0x2e17 0x173d 0x3a6e 0x71bf 0x25f9 0x0a5d
+			0x7c57 0x0fbe 0x46ce 0x4939 0x6b17 0x37bb 0x3e91 0x76db>;
+		onfi,nand-timing-mode = <0x1f>;
+/*
+		main@400000 {
+			label = "main";
+			reg = /bits/ 64 <0x400000 0xffc00000>;
+		};
+*/
+	};
+};
diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
index d4ba772..af89575 100644
--- a/arch/arm/dts/sun7i-a20.dtsi
+++ b/arch/arm/dts/sun7i-a20.dtsi
@@ -612,6 +612,17 @@ 
 			clocks = <&ahb_gates 17>;
 			status = "disabled";
 		};
+		
+		nfc: nand@01c03000 {
+			compatible = "allwinner,sun4i-nand";
+			reg = <0x01c03000 0x1000>;
+			interrupts = <0 37 4>;
+			clocks = <&ahb_gates 13>, <&nand_clk>;
+			clock-names = "ahb", "mod";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 
 		mdio: mdio@01c0b080 {
 			compatible = "allwinner,sun4i-a10-mdio";
@@ -1020,6 +1031,85 @@ 
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
+			nand_pins_a: nand_base0@0 {
+				allwinner,pins = "PC0", "PC1", "PC2",
+						"PC5", "PC8", "PC9", "PC10",
+						"PC11", "PC12", "PC13", "PC14",
+						"PC15", "PC16";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_cs0_pins_a: nand_cs@0 {
+				allwinner,pins = "PC4";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_cs1_pins_a: nand_cs@1 {
+				allwinner,pins = "PC3";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_cs2_pins_a: nand_cs@2 {
+				allwinner,pins = "PC17";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_cs3_pins_a: nand_cs@3 {
+				allwinner,pins = "PC18";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_cs4_pins_a: nand_cs@4 {
+				allwinner,pins = "PC19";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_cs5_pins_a: nand_cs@5 {
+				allwinner,pins = "PC20";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_cs6_pins_a: nand_cs@6 {
+				allwinner,pins = "PC21";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_cs7_pins_a: nand_cs@7 {
+				allwinner,pins = "PC22";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_rb0_pins_a: nand_rb@0 {
+				allwinner,pins = "PC6";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_rb1_pins_a: nand_rb@1 {
+				allwinner,pins = "PC7";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
 		};
 
 		timer@01c20c00 {