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[U-Boot,6/8] arch:arm:fsl: Add XHCI support for LS1021A

Message ID 1432891042-19781-7-git-send-email-ramneek.mehresh@freescale.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

ramneek mehresh May 29, 2015, 9:17 a.m. UTC 
From: ramneek mehresh <ramneek.mehresh@freescale.com>

Add base register address information for USB
XHCI controller on LS1021A

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
 arch/arm/include/asm/arch-ls102xa/config.h        |  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 10 ++++++++++
 2 files changed, 11 insertions(+)

Comments

Tom Rini June 3, 2015, 2:09 p.m. UTC | #1 
On Fri, May 29, 2015 at 02:47:20PM +0530, Ramneek Mehresh wrote:

> From: ramneek mehresh <ramneek.mehresh@freescale.com>
> 
> Add base register address information for USB
> XHCI controller on LS1021A
> 
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

Reviewed-by: Tom Rini <trini@konsulko.com>
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Patch

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 4dc528b..c55cdef 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -35,6 +35,7 @@ 
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
+#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_LS102XA_USB1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index ee547fb..8e5fcdc 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -395,4 +395,14 @@  struct ccsr_cci400 {
 	} pcounter[4];			/* Performance Counter */
 	u8 res_e004[0x10000 - 0xe004];
 };
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE	0x3100000
+#define FSL_OCP1_SCP_BASE	0x4a084c00
+#define FSL_OTG_WRAPPER_BASE	0x4A020000
+
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR	CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR	0
+#define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+					CONFIG_SYS_FSL_XHCI_USB2_ADDR}
 #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */