From patchwork Thu May 28 09:24:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar Kushwaha X-Patchwork-Id: 478620 X-Patchwork-Delegate: yorksun@freescale.com From: prabhakar at freescale.com (Prabhakar Kushwaha) Date: Thu, 28 May 2015 14:54:13 +0530 Subject: [U-Boot] [PATCH 20/22][v2] arm/errata: Update required bits for A57 cores erratas In-Reply-To: <1432805055-1244-1-git-send-email-prabhakar@freescale.com> References: <1432805055-1244-1-git-send-email-prabhakar@freescale.com> Message-ID: <1432805055-1244-20-git-send-email-prabhakar@freescale.com> List-Id: U-Boot discussion From: Bhupesh Sharma This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma Signed-off-by: Dai Haruki Signed-off-by: Prabhakar Kushwaha --- Changes for v2: sending as it is for patch set arch/arm/cpu/armv8/start.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e5f2766..e70bed4 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -115,18 +115,18 @@ apply_a57_core_errata: #ifdef CONFIG_ARM_ERRATA_828024 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable non-allocate hint of w-b-n-a memory type */ - mov x0, #0x1 << 49 + orr x0, x0, #1 << 49 /* Disable write streaming no L1-allocate threshold */ - mov x0, #0x3 << 25 + orr x0, x0, #3 << 25 /* Disable write streaming no-allocate threshold */ - mov x0, #0x3 << 27 + orr x0, x0, #3 << 27 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif #ifdef CONFIG_ARM_ERRATA_826974 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable speculative load execution ahead of a DMB */ - mov x0, #0x1 << 59 + orr x0, x0, #1 << 59 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif