From patchwork Wed May 27 05:35:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 476925 X-Patchwork-Delegate: yamada.m@jp.panasonic.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BEAAB1401B5 for ; Wed, 27 May 2015 15:36:25 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0B3B74B667; Wed, 27 May 2015 07:36:02 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KA-y-T81pxhU; Wed, 27 May 2015 07:36:01 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 35A184B64D; Wed, 27 May 2015 07:35:43 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 445834A033 for ; Wed, 27 May 2015 07:35:31 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KfB3KBPYWGx1 for ; Wed, 27 May 2015 07:35:31 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg010-v.nifty.com (conuserg010.nifty.com [202.248.44.36]) by theia.denx.de (Postfix) with ESMTPS id 6A6DC4B622 for ; Wed, 27 May 2015 07:35:25 +0200 (CEST) Received: from beagle.diag.org (KD111237140023.au-net.ne.jp [111.237.140.23]) (authenticated) by conuserg010-v.nifty.com with ESMTP id t4R5Z39d003157; Wed, 27 May 2015 14:35:13 +0900 X-Nifty-SrcIP: [111.237.140.23] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 27 May 2015 14:35:17 +0900 Message-Id: <1432704917-17493-8-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432704917-17493-1-git-send-email-yamada.masahiro@socionext.com> References: <1432704917-17493-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH v2 7/7] ARM: UniPhier: update DDR PHY register map for PH1-Pro5 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" PH1-Pro5 includes a newer version of DDR PHY IP. Some registers have been added to the reserved areas. Signed-off-by: Masahiro Yamada --- Changes in v2: None arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index 6b7d600..df7d815 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -1,8 +1,9 @@ /* * UniPhier DDR PHY registers * - * Copyright (C) 2014 Panasonic Corporation - * Author: Masahiro Yamada + * Copyright (C) 2014-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ @@ -37,7 +38,10 @@ struct ddrphy { u32 dtar[4]; /* Data Training Address Register */ u32 dtdr[2]; /* Data Training Data Register */ u32 dtedr[2]; /* Data Training Eye Data Register */ - u32 rsv0[13]; /* Reserved */ + u32 pgcr2; /* PHY General Configuration Register 2 */ + u32 rsv0[8]; /* Reserved */ + u32 rdimmgcr[2]; /* RDIMM General Configuration Register */ + u32 rdimmcr0[2]; /* RDIMM Control Register */ u32 dcuar; /* DCU Address Register */ u32 dcudr; /* DCU Data Register */ u32 dcurr; /* DCU Run Register */ @@ -70,7 +74,8 @@ struct ddrphy { u32 lcdlr[3]; /* Local Calibrated Delay Line Register */ u32 mdlr; /* Master Delay Line Register */ u32 gtr; /* General Timing Register */ - u32 rsv[3]; /* Reserved */ + u32 gsr2; /* General Status Register 2 */ + u32 rsv[2]; /* Reserved */ } dx[9]; };