From patchwork Tue May 26 15:00:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roy Spliet X-Patchwork-Id: 476502 X-Patchwork-Delegate: hdegoede@redhat.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5AF1B1402A2 for ; Wed, 27 May 2015 01:01:34 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 695AA4B7FB; Tue, 26 May 2015 17:01:21 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WP2_3Om8zo3K; Tue, 26 May 2015 17:01:21 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A3A634B7F0; Tue, 26 May 2015 17:01:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 251A64B7DC for ; Tue, 26 May 2015 17:01:07 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qNGaKQSRVOFv for ; Tue, 26 May 2015 17:01:07 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f176.google.com (mail-wi0-f176.google.com [209.85.212.176]) by theia.denx.de (Postfix) with ESMTPS id 6465D4B7D6 for ; Tue, 26 May 2015 17:00:58 +0200 (CEST) Received: by wichy4 with SMTP id hy4so85349699wic.1 for ; Tue, 26 May 2015 08:00:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:to:cc:subject:date:message-id :in-reply-to:references:content-type; bh=LorRmOK4c/xt4j+CLNE/EUGRQuj/atal1svVtLuoZjc=; b=IcP/Kn8y1Sqdd6HTN1d+JrACQ7a4XP8aIG0GCx7a8r3I41qiJi1cpkW+8wEbfy7jeS vRP9rjchkbD+P47iyMllruSU32//rM+/Q/CPUg04VSdsBfvOfGxjXQHTrO9oX1G2ytEu Wf5gNV1FTh9xQ9gIiijekQGSThR6QSv+kvyMKOtjFHS09MXuDy0WoVNGTaWtBNspTCeh BQfZTwgJykrm6c/iHKaeVD3B+a7n25LB5HZpTqqQuxLAkqXcwS9rvH9nOk9xT1IE2H1K BvsPUMbCr1faYA2En2xQNpqM0uvNQgOo6daXUk6d94bx8KPsv5ROq6U54fosH9rxokO8 RA5A== X-Gm-Message-State: ALoCoQm2/B96+CT7MdKaMSRZzFqOmITeQAdDsFhQ3t2yHDOfzG4anv8lv7CL01Ymiq45PyDtEgMrWtXVbqv+3nuuNz55NURChKxskEHxIYsCEY/jWptyWN4T0Ru7LXBvSGVrgyqyJCrS MIME-Version: 1.0 X-Received: by 10.180.208.99 with SMTP id md3mr41721571wic.34.1432652458428; Tue, 26 May 2015 08:00:58 -0700 (PDT) Received: from Seven.fritz.box (a83-163-237-212.adsl.xs4all.nl. [83.163.237.212]) by mx.google.com with ESMTPSA id f8sm17309019wiy.7.2015.05.26.08.00.56 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 May 2015 08:00:57 -0700 (PDT) From: Roy Spliet To: Hans de Goede , Linux Sunxi , U-Boot mailinglist , Daniel Kochmanski , Ian Campbell Date: Tue, 26 May 2015 17:00:41 +0200 Message-Id: <1432652442-25043-4-git-send-email-r.spliet@ultimaker.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1432652442-25043-1-git-send-email-r.spliet@ultimaker.com> References: <1432652442-25043-1-git-send-email-r.spliet@ultimaker.com> Cc: Roy Spliet Subject: [U-Boot] [PATCH V4 3/4] sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMA X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" V4: - Match clock_sun9i too - Make sure definitions for DMA gate bits are available across boards Signed-off-by: Roy Spliet --- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 4 ++-- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 3 +++ arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 6 +++++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index c28ee05..e40d368 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -39,7 +39,7 @@ struct sunxi_ccm_reg { u32 apb0_gate; /* 0x68 apb0 module clock gating */ u32 apb1_gate; /* 0x6c apb1 module clock gating */ u8 res4[0x10]; - u32 nand_sclk_cfg; /* 0x80 nand sub clock control */ + u32 nand0_clk_cfg; /* 0x80 nand sub clock control */ u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ @@ -177,7 +177,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_ACE 16 #define AHB_GATE_OFFSET_DLL 15 #define AHB_GATE_OFFSET_SDRAM 14 -#define AHB_GATE_OFFSET_NAND 13 +#define AHB_GATE_OFFSET_NAND0 13 #define AHB_GATE_OFFSET_MS 12 #define AHB_GATE_OFFSET_MMC3 11 #define AHB_GATE_OFFSET_MMC2 10 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 04c6d58..7ba818f 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -215,11 +215,14 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB0 24 #define AHB_GATE_OFFSET_MCTL 14 #define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_NAND0 13 +#define AHB_GATE_OFFSET_NAND1 12 #define AHB_GATE_OFFSET_MMC3 11 #define AHB_GATE_OFFSET_MMC2 10 #define AHB_GATE_OFFSET_MMC1 9 #define AHB_GATE_OFFSET_MMC0 8 #define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +#define AHB_GATE_OFFSET_DMA 6 #define AHB_GATE_OFFSET_SS 5 /* ahb_gate1 offsets */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index c506b0a..a61934f 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -42,7 +42,7 @@ struct sunxi_ccm_reg { u32 clk_output_b; /* 0x184 clk_output_a */ u8 reserved5[0x278]; /* 0x188 */ - u32 nand0_clk_cfg0; /* 0x400 nand0 clock configuration0 */ + u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */ u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */ u8 reserved6[0x08]; /* 0x408 */ u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */ @@ -113,8 +113,12 @@ struct sunxi_ccm_reg { /* ahb_gate0 fields */ /* On sun9i all sdc-s share their ahb gate, so ignore (x) */ +#define AHB_GATE_OFFSET_NAND0 13 #define AHB_GATE_OFFSET_MMC(x) 8 +/* ahb gate1 field */ +#define AHB_GATE_OFFSET_DMA 24 + /* apb1_gate fields */ #define APB1_GATE_UART_SHIFT 16 #define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)