From patchwork Mon May 18 13:06:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhuvanchandra DV X-Patchwork-Id: 473385 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 48AAB1401B5 for ; Mon, 18 May 2015 23:26:01 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3637B4B78B; Mon, 18 May 2015 15:25:29 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jP5szmkkjcUx; Mon, 18 May 2015 15:25:29 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EA4A54B79B; Mon, 18 May 2015 15:25:05 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8EACB4B6F5 for ; Mon, 18 May 2015 15:23:06 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5T0t8MpqasNb for ; Mon, 18 May 2015 15:23:06 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from emea01-am1-obe.outbound.protection.outlook.com (mail-am1on0106.outbound.protection.outlook.com [157.56.112.106]) by theia.denx.de (Postfix) with ESMTPS id 20EA54B6F4 for ; Mon, 18 May 2015 15:23:03 +0200 (CEST) Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=bhuvanchandra.dv@toradex.com; Received: from tdx.toradex.int (115.115.225.206) by DB4PR05MB271.eurprd05.prod.outlook.com (10.242.158.26) with Microsoft SMTP Server (TLS) id 15.1.166.22; Mon, 18 May 2015 13:07:42 +0000 From: Bhuvanchandra DV To: , Date: Mon, 18 May 2015 18:36:23 +0530 Message-ID: <1431954389-6433-6-git-send-email-bhuvanchandra.dv@toradex.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1431954389-6433-1-git-send-email-bhuvanchandra.dv@toradex.com> References: <1431954389-6433-1-git-send-email-bhuvanchandra.dv@toradex.com> MIME-Version: 1.0 X-Originating-IP: [115.115.225.206] X-ClientProxiedBy: HKXPR03CA0082.apcprd03.prod.outlook.com (25.163.104.40) To DB4PR05MB271.eurprd05.prod.outlook.com (10.242.158.26) X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DB4PR05MB271; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:DB4PR05MB271; BCL:0; PCL:0; RULEID:; SRVR:DB4PR05MB271; X-Forefront-PRVS: 058043A388 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10019020)(6009001)(199003)(189002)(66066001)(47776003)(86362001)(77096005)(50466002)(107886002)(50986999)(64706001)(5001830100001)(5001860100001)(189998001)(76176999)(5001960100002)(69596002)(2950100001)(122386002)(97736004)(40100003)(36756003)(77156002)(4001540100001)(19580395003)(62966003)(19580405001)(81156007)(68736005)(33646002)(92566002)(229853001)(46102003)(87976001)(106356001)(42186005)(101416001)(53416004)(50226001)(5001770100001)(105586002)(48376002)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:DB4PR05MB271; H:tdx.toradex.int; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; Received-SPF: None (protection.outlook.com: toradex.com does not designate permitted sender hosts) X-OriginatorOrg: toradex.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2015 13:07:42.9756 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR05MB271 X-Mailman-Approved-At: Mon, 18 May 2015 15:24:37 +0200 Cc: marex@denx.de, trini@konsulko.com, Bhuvanchandra DV , marcel@ziswiler.com Subject: [U-Boot] [PATCH 05/11] arm: vf610: Add clock support for DSPI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Bhuvanchandra DV --- arch/arm/cpu/armv7/vf610/generic.c | 7 +++++++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 1bb9b8e..05c401d 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -198,6 +198,11 @@ static u32 get_i2c_clk(void) return get_ipg_clk(); } +static u32 get_dspi_clk(void) +{ + return get_ipg_clk(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -215,6 +220,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_fec_clk(); case MXC_I2C_CLK: return get_i2c_clk(); + case MXC_DSPI_CLK: + return get_dspi_clk(); default: break; } diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h index 535adad..e5a5c6d 100644 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -17,6 +17,7 @@ enum mxc_clock { MXC_ESDHC_CLK, MXC_FEC_CLK, MXC_I2C_CLK, + MXC_DSPI_CLK, }; void enable_ocotp_clk(unsigned char enable); diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index bc6db2a..fdb45e9 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -189,6 +189,8 @@ struct anadig_reg { #define CCM_REG_CTRL_MASK 0xffffffff #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) +#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) #define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) @@ -206,6 +208,8 @@ struct anadig_reg { #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) #define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26) #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) #define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)