From patchwork Thu May 14 05:08:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 472215 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C6AA21402B3 for ; Thu, 14 May 2015 15:09:02 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A75FF4A039; Thu, 14 May 2015 07:08:59 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Fmg4lEhXH7Wc; Thu, 14 May 2015 07:08:59 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A05D54B616; Thu, 14 May 2015 07:08:58 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BBB1B4B617 for ; Thu, 14 May 2015 07:08:55 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pTxObbYT8AUM for ; Thu, 14 May 2015 07:08:55 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f170.google.com (mail-pd0-f170.google.com [209.85.192.170]) by theia.denx.de (Postfix) with ESMTPS id 388C54B616 for ; Thu, 14 May 2015 07:08:52 +0200 (CEST) Received: by pdbnk13 with SMTP id nk13so73591805pdb.0 for ; Wed, 13 May 2015 22:08:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=20c4/0whypaYchfUMpuqCGAOxzX6pShpU+zkw/qqmOM=; b=fCacOnvob8sCOjIeQdsdYxGyevS5zk0Z2ZOos0vyYr774SQUW2id3uG4Q/hXUa86HL wYVWel0YXndLKQ4f8wmEy624yZUvc7HHxU05yMlSkgXhs0opR1d9Gpr1PtpjD+dcXQt3 J2Db7aFyM26aROmQbvg0VYkr9IAZ3K7xAFi/WgpSO/PjgsToiPWQ3jZkLaBf9h2mbL9p tM9/tAXaeuOi6BZ/c94ct5MdDGvf4eYYwrzelVZwr/iHB2b+haB8HMRIOUtWlh5+u4Wz EQnnM5doS011jaJEp5Qo7NogsaLmsQIIjHs0Ng0hmxaLsEuJvxs5FcI3Ejzzg5YmyO66 /uCg== X-Gm-Message-State: ALoCoQl1hAO2a69XHP6mzqKuKc1RkpLpE8xs8pRMUZT29svMBZClCdlv3K1XlSBBYRKROBjcoRKJ X-Received: by 10.66.186.103 with SMTP id fj7mr4486628pac.132.1431580130513; Wed, 13 May 2015 22:08:50 -0700 (PDT) Received: from tharvey.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id g4sm20922581pdk.82.2015.05.13.22.08.49 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 May 2015 22:08:49 -0700 (PDT) From: Tim Harvey To: Stefano Babic Date: Wed, 13 May 2015 22:08:40 -0700 Message-Id: <1431580121-24726-2-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431580121-24726-1-git-send-email-tharvey@gateworks.com> References: <1431580121-24726-1-git-send-email-tharvey@gateworks.com> Cc: Fabio Estevam , Jon Nettleton , u-boot@lists.denx.de, Ye Li , Stefan Roese , Markus Niebel Subject: [U-Boot] [PATCH v2 1/2] imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description Table. Return this frequency so that it can be used elsewhere. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades. Signed-off-by: Tim Harvey Tested-by: Nikolay Dimitrov --- arch/arm/cpu/armv7/mx6/soc.c | 41 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + 2 files changed, 42 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index dd34138..71fa1fb 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -83,6 +83,47 @@ u32 get_cpu_rev(void) return (type << 12) | (reg + 0x10); } +/* + * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440) + * defines a 2-bit SPEED_GRADING + */ +#define OCOTP_CFG3_SPEED_SHIFT 16 +#define OCOTP_CFG3_SPEED_800MHZ 0 +#define OCOTP_CFG3_SPEED_850MHZ 1 +#define OCOTP_CFG3_SPEED_1GHZ 2 +#define OCOTP_CFG3_SPEED_1P2GHZ 3 + +u32 get_cpu_speed_grade_hz(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + uint32_t val; + + val = readl(&fuse->cfg3); + val >>= OCOTP_CFG3_SPEED_SHIFT; + val &= 0x3; + + switch (val) { + /* Valid for IMX6DQ */ + case OCOTP_CFG3_SPEED_1P2GHZ: + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + return 1200000000; + /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ + case OCOTP_CFG3_SPEED_1GHZ: + return 996000000; + /* Valid for IMX6DQ */ + case OCOTP_CFG3_SPEED_850MHZ: + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + return 852000000; + /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ + case OCOTP_CFG3_SPEED_800MHZ: + return 792000000; + } + return 0; +} + #ifdef CONFIG_REVISION_TAG u32 __weak get_board_rev(void) { diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 28ba844..a2cd0a9 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -16,6 +16,7 @@ u32 get_nr_cpus(void); u32 get_cpu_rev(void); +u32 get_cpu_speed_grade_hz(void); /* returns MXC_CPU_ value */ #define cpu_type(rev) (((rev) >> 12)&0xff)