From patchwork Wed May 13 13:02:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 471871 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 63559140758 for ; Wed, 13 May 2015 23:03:47 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E4DD04B7BC; Wed, 13 May 2015 15:03:34 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TpVm0jn0nhKE; Wed, 13 May 2015 15:03:34 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 720D94B760; Wed, 13 May 2015 15:03:14 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 05ABE4B71D for ; Wed, 13 May 2015 15:03:04 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5hV-YaqwHCUA for ; Wed, 13 May 2015 15:03:03 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-oi0-f74.google.com (mail-oi0-f74.google.com [209.85.218.74]) by theia.denx.de (Postfix) with ESMTPS id 3078E4B734 for ; Wed, 13 May 2015 15:02:58 +0200 (CEST) Received: by oiax69 with SMTP id x69so2332764oia.1 for ; Wed, 13 May 2015 06:02:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w5OHzVDeUgaXPyUZNIzDAt9krVw+dFWOosZCvKhWxjs=; b=AKdkmdc3s9Kto+77y5sVQgE7z9XK1ERVFvAh9iVuYl9jCBcuy1opbpb+7RAk7yC/i7 6TxWv6Bodhwjdl+W5+ZBs6ZChBmr5Gb8KnUPYmtRPePi0PTDzYKWKkEsiaO1/1hgd+9p F/0P/xMBxGM5m3HPb9eRBzjL/pg5lyb3x25tQ/TkxSGXXjLVMaIhL6zVdvnIBxcC1q7Z /MBHulrg1lQslKTlkwa0lLLsNAawfj1868ZjYQNGTQRCpHxJkU4aHvnjEIBOvgGRR0Vx 2Hfb/nfEhKQbOLmL0EebszzNlG6dvqeZCvb9XcUA1FpjSscoZr7eCeVJ5VihBIVLZSV+ 8tGA== X-Gm-Message-State: ALoCoQnPMw0PEw0yYXtCRsDNe7zTLUEyGJYJPITWjAplQKTiOTnu2scuBcjXvZVC6jjZKDEWp9vS X-Received: by 10.42.151.195 with SMTP id f3mr11033343icw.8.1431522177730; Wed, 13 May 2015 06:02:57 -0700 (PDT) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id i27si1075360yha.6.2015.05.13.06.02.57 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 May 2015 06:02:57 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id zFJDI85f.1; Wed, 13 May 2015 06:02:57 -0700 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 0F03D2212C5; Wed, 13 May 2015 07:02:57 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Wed, 13 May 2015 07:02:30 -0600 Message-Id: <1431522151-20245-9-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1431522151-20245-1-git-send-email-sjg@chromium.org> References: <1431522151-20245-1-git-send-email-sjg@chromium.org> Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH v2 8/9] tegra: nyan-big: Allow TPM on I2C X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable the I2C3 pins so that the TPM can be used. Note: There is an DP change also, caused by running board-to-uboot.py script in the latest tegra-pinmux-script tree. Signed-off-by: Simon Glass Acked-by: Stephen Warren --- Changes in v2: - Use tegra-pinmux-scripts to update the pinmux board/nvidia/nyan-big/pinmux-config-nyan-big.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h index 9c5fbaa..9c838ba 100644 --- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h +++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -234,8 +234,8 @@ static const struct pmux_pingrp_config nyan_big_pingrps[] = { PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(CAM_I2C_SCL_PBB1, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_I2C_SDA_PBB2, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), @@ -257,7 +257,7 @@ static const struct pmux_pingrp_config nyan_big_pingrps[] = { PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),