| Message ID | 1429974275-13743-2-git-send-email-sjg@chromium.org |
|---|---|
| State | Superseded |
| Delegated to: | Simon Glass |
| Headers | show |
Hi Simon, On Sat, Apr 25, 2015 at 11:04 PM, Simon Glass <sjg@chromium.org> wrote: > Now that reset_cpu() functions correctly, use it instead of directly > accessing the port. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > arch/x86/cpu/ivybridge/cpu.c | 5 ++--- > arch/x86/cpu/ivybridge/early_me.c | 7 +++---- > arch/x86/cpu/ivybridge/sdram.c | 3 +-- > 3 files changed, 6 insertions(+), 9 deletions(-) > > diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c > index 37f3731..a62b30e 100644 > --- a/arch/x86/cpu/ivybridge/cpu.c > +++ b/arch/x86/cpu/ivybridge/cpu.c > @@ -92,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void) > > /* Issue warm reset, will be "CPU only" due to soft reset data */ > outb(0x0, PORT_RESET); > - outb(0x6, PORT_RESET); > + outb(SYS_RST | RST_CPU, PORT_RESET); > cpu_hlt(); > > /* Not reached */ > @@ -286,8 +286,7 @@ int print_cpuinfo(void) > > /* System is not happy after keyboard reset... */ > debug("Issuing CF9 warm reset\n"); > - outb(0x6, 0xcf9); > - cpu_hlt(); > + reset_cpu(); > } > > /* Early chipset init required before RAM init can work */ > diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c > index 356bbb4..0347197 100644 > --- a/arch/x86/cpu/ivybridge/early_me.c > +++ b/arch/x86/cpu/ivybridge/early_me.c > @@ -183,9 +183,8 @@ int intel_early_me_init_done(u8 status) > } > > /* Perform the requested reset */ > - if (reset) { > - outb(reset, 0xcf9); > - cpu_hlt(); > - } > + if (reset) > + reset_cpu(); > + I think the following codes before this code block need to be updated to use the reset bit enum to assign to the reset variable. reset = 0; switch (hfs.ack_data) { case ME_HFS_ACK_CONTINUE: /* Continue to boot */ return 0; case ME_HFS_ACK_RESET: /* Non-power cycle reset */ set_global_reset(0); reset = 0x06; break; case ME_HFS_ACK_PWR_CYCLE: /* Power cycle reset */ set_global_reset(0); reset = 0x0e; break; case ME_HFS_ACK_GBL_RESET: /* Global reset */ set_global_reset(1); reset = 0x0e; break; > return -1; > } > diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c > index 9a6da37..42e1e60 100644 > --- a/arch/x86/cpu/ivybridge/sdram.c > +++ b/arch/x86/cpu/ivybridge/sdram.c > @@ -393,8 +393,7 @@ int sdram_initialise(struct pei_data *pei_data) > /* If MRC data is not found we cannot continue S3 resume. */ > if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { > debug("Giving up in sdram_initialize: No MRC data\n"); > - outb(0x6, PORT_RESET); > - cpu_hlt(); > + reset_cpu(); > } > > /* Pass console handler in pei_data */ > -- Regards, Bin
Hi Bin, On 26 April 2015 at 22:58, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi Simon, > > On Sat, Apr 25, 2015 at 11:04 PM, Simon Glass <sjg@chromium.org> wrote: >> Now that reset_cpu() functions correctly, use it instead of directly >> accessing the port. >> >> Signed-off-by: Simon Glass <sjg@chromium.org> >> --- >> >> arch/x86/cpu/ivybridge/cpu.c | 5 ++--- >> arch/x86/cpu/ivybridge/early_me.c | 7 +++---- >> arch/x86/cpu/ivybridge/sdram.c | 3 +-- >> 3 files changed, 6 insertions(+), 9 deletions(-) >> >> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c >> index 37f3731..a62b30e 100644 >> --- a/arch/x86/cpu/ivybridge/cpu.c >> +++ b/arch/x86/cpu/ivybridge/cpu.c >> @@ -92,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void) >> >> /* Issue warm reset, will be "CPU only" due to soft reset data */ >> outb(0x0, PORT_RESET); >> - outb(0x6, PORT_RESET); >> + outb(SYS_RST | RST_CPU, PORT_RESET); >> cpu_hlt(); >> >> /* Not reached */ >> @@ -286,8 +286,7 @@ int print_cpuinfo(void) >> >> /* System is not happy after keyboard reset... */ >> debug("Issuing CF9 warm reset\n"); >> - outb(0x6, 0xcf9); >> - cpu_hlt(); >> + reset_cpu(); >> } >> >> /* Early chipset init required before RAM init can work */ >> diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c >> index 356bbb4..0347197 100644 >> --- a/arch/x86/cpu/ivybridge/early_me.c >> +++ b/arch/x86/cpu/ivybridge/early_me.c >> @@ -183,9 +183,8 @@ int intel_early_me_init_done(u8 status) >> } >> >> /* Perform the requested reset */ >> - if (reset) { >> - outb(reset, 0xcf9); >> - cpu_hlt(); >> - } >> + if (reset) >> + reset_cpu(); >> + > > I think the following codes before this code block need to be updated > to use the reset bit enum to assign to the reset variable. Ah yes, I didn't look very hard. I'll fix this. > > reset = 0; > switch (hfs.ack_data) { > case ME_HFS_ACK_CONTINUE: > /* Continue to boot */ > return 0; > case ME_HFS_ACK_RESET: > /* Non-power cycle reset */ > set_global_reset(0); > reset = 0x06; > break; > case ME_HFS_ACK_PWR_CYCLE: > /* Power cycle reset */ > set_global_reset(0); > reset = 0x0e; > break; > case ME_HFS_ACK_GBL_RESET: > /* Global reset */ > set_global_reset(1); > reset = 0x0e; > break; > >> return -1; >> } >> diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c >> index 9a6da37..42e1e60 100644 >> --- a/arch/x86/cpu/ivybridge/sdram.c >> +++ b/arch/x86/cpu/ivybridge/sdram.c >> @@ -393,8 +393,7 @@ int sdram_initialise(struct pei_data *pei_data) >> /* If MRC data is not found we cannot continue S3 resume. */ >> if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { >> debug("Giving up in sdram_initialize: No MRC data\n"); >> - outb(0x6, PORT_RESET); >> - cpu_hlt(); >> + reset_cpu(); >> } >> >> /* Pass console handler in pei_data */ >> -- Regards, Simon
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 37f3731..a62b30e 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -92,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void) /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, PORT_RESET); - outb(0x6, PORT_RESET); + outb(SYS_RST | RST_CPU, PORT_RESET); cpu_hlt(); /* Not reached */ @@ -286,8 +286,7 @@ int print_cpuinfo(void) /* System is not happy after keyboard reset... */ debug("Issuing CF9 warm reset\n"); - outb(0x6, 0xcf9); - cpu_hlt(); + reset_cpu(); } /* Early chipset init required before RAM init can work */ diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index 356bbb4..0347197 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -183,9 +183,8 @@ int intel_early_me_init_done(u8 status) } /* Perform the requested reset */ - if (reset) { - outb(reset, 0xcf9); - cpu_hlt(); - } + if (reset) + reset_cpu(); + return -1; } diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 9a6da37..42e1e60 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -393,8 +393,7 @@ int sdram_initialise(struct pei_data *pei_data) /* If MRC data is not found we cannot continue S3 resume. */ if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { debug("Giving up in sdram_initialize: No MRC data\n"); - outb(0x6, PORT_RESET); - cpu_hlt(); + reset_cpu(); } /* Pass console handler in pei_data */
Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> --- arch/x86/cpu/ivybridge/cpu.c | 5 ++--- arch/x86/cpu/ivybridge/early_me.c | 7 +++---- arch/x86/cpu/ivybridge/sdram.c | 3 +-- 3 files changed, 6 insertions(+), 9 deletions(-)