From patchwork Thu Apr 2 19:14:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Brinsko X-Patchwork-Id: 458380 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 529C6140142 for ; Mon, 6 Apr 2015 23:10:44 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1ED53B37BA; Mon, 6 Apr 2015 15:10:38 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kuSzudJdZRjb; Mon, 6 Apr 2015 15:10:38 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 850B5B37BE; Mon, 6 Apr 2015 15:10:28 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 900DCB37B1 for ; Thu, 2 Apr 2015 21:26:02 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id L7fdev-0AafX for ; Thu, 2 Apr 2015 21:26:02 +0200 (CEST) X-Greylist: delayed 643 seconds by postgrey-1.34 at theia; Thu, 02 Apr 2015 21:25:58 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch3vs02.rockwellcollins.com (ch3vs02.rockwellcollins.com [205.175.226.29]) by theia.denx.de (Postfix) with ESMTPS id 0F8F24B624 for ; Thu, 2 Apr 2015 21:25:58 +0200 (CEST) Received: from ofwch3n02.rockwellcollins.com (HELO crulimr01.rockwellcollins.com) ([205.175.226.14]) by ch3vs02.rockwellcollins.com with ESMTP; 02 Apr 2015 14:15:14 -0500 X-Received: from smtplb.rockwellcollins.com (smtplb.rockwellcollins.com [131.198.63.134]) by crulimr01.rockwellcollins.com (Postfix) with ESMTP id 0A5AE601DA; Thu, 2 Apr 2015 14:15:14 -0500 (CDT) X-Received: from thehammer.rockwellcollins.com (unknown [192.168.141.197]) by smtplb.rockwellcollins.com (Postfix) with ESMTP id EE3EB801F4; Thu, 2 Apr 2015 14:15:13 -0500 (CDT) From: Bryan Brinsko To: u-boot@lists.denx.de Date: Thu, 2 Apr 2015 14:14:00 -0500 Message-Id: <1428002040-64396-1-git-send-email-bryan.brinsko@rockwellcollins.com> X-Mailer: git-send-email 1.9.1 X-Mailman-Approved-At: Mon, 06 Apr 2015 15:10:22 +0200 Cc: Marek Vasut , Bryan Brinsko Subject: [U-Boot] [PATCH 1/1] ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko Cc: Albert Aribaud Cc: Marek Vasut --- arch/arm/include/asm/system.h | 37 +++++++++++++++++++++++++++++++++++++ arch/arm/lib/cache-cp15.c | 14 ++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 2a5bed2..9cd2f1e 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -196,6 +196,28 @@ static inline void set_dacr(unsigned int val) isb(); } +#ifdef CONFIG_ARMV7 +/* Short-Descriptor Translation Table Level 1 Bits */ +#define TTB_SECT_NS_MASK (1 << 19) +#define TTB_SECT_NG_MASK (1 << 17) +#define TTB_SECT_S_MASK (1 << 16) +/* Note: TTB AP bits are set elsewhere */ +#define TTB_SECT_TEX(x) ((x & 0x7) << 12) +#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) +#define TTB_SECT_XN_MASK (1 << 4) +#define TTB_SECT_C_MASK (1 << 3) +#define TTB_SECT_B_MASK (1 << 2) +#define TTB_SECT (2 << 0) + +/* options available for data cache on each page */ +enum dcache_option { + DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) | + TTB_SECT_XN_MASK | TTB_SECT, + DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, + DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, + DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), +}; +#else /* options available for data cache on each page */ enum dcache_option { DCACHE_OFF = 0x12, @@ -203,6 +225,7 @@ enum dcache_option { DCACHE_WRITEBACK = 0x1e, DCACHE_WRITEALLOC = 0x16, }; +#endif /* Size of an MMU section */ enum { @@ -210,6 +233,20 @@ enum { MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, }; +#ifdef CONFIG_ARMV7 +/* TTBR0 bits */ +#define TTBR0_BASE_ADDR_MASK 0xFFFFC000 +#define TTBR0_RGN_NC (0 << 3) +#define TTBR0_RGN_WBWA (1 << 3) +#define TTBR0_RGN_WT (2 << 3) +#define TTBR0_RGN_WB (3 << 3) +/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ +#define TTBR0_IRGN_NC (0 << 0 | 0 << 6) +#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) +#define TTBR0_IRGN_WT (1 << 0 | 0 << 6) +#define TTBR0_IRGN_WB (1 << 0 | 1 << 6) +#endif + /** * Change the cache settings for a region. * diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0291afa..c65e068 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -96,9 +96,23 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); } +#ifdef CONFIG_ARMV7 + /* Set TTBR0 */ + reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT; +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) + reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA; +#else + reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB; +#endif + asm volatile("mcr p15, 0, %0, c2, c0, 0" + : : "r" (reg) : "memory"); +#else /* Copy the page table address to cp15 */ asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (gd->arch.tlb_addr) : "memory"); +#endif /* Set the access control to all-supervisor */ asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (~0));