From patchwork Tue Mar 24 19:25:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 453994 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D04DF14011D for ; Wed, 25 Mar 2015 06:27:20 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 21ABF4B62B; Tue, 24 Mar 2015 20:27:15 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ESsfAG_ZpOHb; Tue, 24 Mar 2015 20:27:14 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 54E03A7422; Tue, 24 Mar 2015 20:27:10 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AF6A34A033 for ; Tue, 24 Mar 2015 20:27:05 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rg286LZVCDLC for ; Tue, 24 Mar 2015 20:27:05 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1on0118.outbound.protection.outlook.com [157.56.110.118]) by theia.denx.de (Postfix) with ESMTPS id 2E6E64A02E for ; Tue, 24 Mar 2015 20:27:02 +0100 (CET) Received: from BY2PR03CA001.namprd03.prod.outlook.com (10.255.93.18) by BLUPR03MB150.namprd03.prod.outlook.com (10.255.212.18) with Microsoft SMTP Server (TLS) id 15.1.106.15; Tue, 24 Mar 2015 19:26:59 +0000 Received: from BN1AFFO11OLC002.protection.gbl (10.255.93.4) by BY2PR03CA001.outlook.office365.com (10.255.93.18) with Microsoft SMTP Server (TLS) id 15.1.125.19 via Frontend Transport; Tue, 24 Mar 2015 19:26:57 +0000 Received: from tx30smr01.am.freescale.net ([192.88.168.50]) by BN1AFFO11OLC002.mail.protection.outlook.com ([10.58.53.73]) with Microsoft SMTP Server (TLS) id 15.1.130.10 via Frontend Transport; Tue, 24 Mar 2015 19:26:56 +0000 Received: from oslab-l1.am.freescale.net ([10.214.87.157]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t2OJQrVl013149; Tue, 24 Mar 2015 12:26:55 -0700 From: York Sun To: Date: Tue, 24 Mar 2015 12:25:09 -0700 Message-ID: <1427225109-2011-2-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1427225109-2011-1-git-send-email-yorksun@freescale.com> References: <1427225109-2011-1-git-send-email-yorksun@freescale.com> X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=yorksun@freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(189002)(199003)(92566002)(62966003)(106466001)(87936001)(86362001)(450100001)(77096005)(48376002)(50226001)(46102003)(2950100001)(36756003)(77156002)(50466002)(110136001)(19580395003)(19580405001)(105606002)(47776003)(33646002)(76176999)(2351001)(229853001)(85426001)(50986999)(217873001); DIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR03MB150; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB150; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(5002010); SRVR:BLUPR03MB150; BCL:0; PCL:0; RULEID:; SRVR:BLUPR03MB150; X-Forefront-PRVS: 0525BB0ADF X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2015 19:26:56.9408 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB150 Cc: Scott Wood , York Sun Subject: [U-Boot] [PATCH v7 26/28] armv8/ls2085ardb: Enable NAND SPL support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Scott Wood Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood Signed-off-by: York Sun --- Changes in v7: Move NAND boot instruction to fsl-lsch3/README. Update board setting to put RCW and u-boot in different NAND block. Changes in v6: None Changes in v5: Fix signed-off-by signature Update LS2085ARDB README to include instructions to form NAND image Changes in v4: Update MAINTAINERS file Changes in v3: None Changes in v2: None arch/arm/Kconfig | 1 + board/freescale/ls2085ardb/MAINTAINERS | 1 + board/freescale/ls2085ardb/ddr.c | 4 ++++ configs/ls2085ardb_nand_defconfig | 4 ++++ include/configs/ls2085ardb.h | 40 ++++++++++++++++++++++++++++---- 5 files changed, 45 insertions(+), 5 deletions(-) create mode 100644 configs/ls2085ardb_nand_defconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f73541c..cf291c8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -663,6 +663,7 @@ config TARGET_LS2085ARDB bool "Support ls2085ardb" select ARM64 select ARMV8_MULTIENTRY + select SUPPORT_SPL help Support for Freescale LS2085ARDB platform. The LS2085A Reference design board (RDB) is a high-performance diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS index 436039f..d5cce40 100644 --- a/board/freescale/ls2085ardb/MAINTAINERS +++ b/board/freescale/ls2085ardb/MAINTAINERS @@ -5,3 +5,4 @@ F: board/freescale/ls2085ardb/ F: board/freescale/ls2085a/ls2085ardb.c F: include/configs/ls2085ardb.h F: configs/ls2085ardb_defconfig +F: configs/ls2085ardb_nand_defconfig diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c index 6cd5e8b..8d71ae1 100644 --- a/board/freescale/ls2085ardb/ddr.c +++ b/board/freescale/ls2085ardb/ddr.c @@ -147,9 +147,13 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + return fsl_ddr_sdram_size(); +#else puts("Initializing DDR....using SPD\n"); dram_size = fsl_ddr_sdram(); +#endif return dram_size; } diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig new file mode 100644 index 0000000..39ba8c5 --- /dev/null +++ b/configs/ls2085ardb_nand_defconfig @@ -0,0 +1,4 @@ ++S:CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" ++S:CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS2085ARDB=y diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index 0a5873b..ae5c2a9 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -139,11 +139,13 @@ unsigned long get_board_sys_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RST_CTL_RESET_EN 0x30 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RCW_SRC_NAND 0x119 #define QIXIS_RST_FORCE_MEM 0x01 #define CONFIG_SYS_CSPR3_EXT (0x0) @@ -169,6 +171,33 @@ unsigned long get_board_sys_clk(void); FTIM2_GPCM_TWP(0x3E)) #define CONFIG_SYS_CS3_FTIM3 0x0 +#if defined(CONFIG_SPL) && defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (2048 * 1024) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SPL_PAD_TO 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR @@ -187,6 +216,12 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x2000 +#endif + /* Debug Server firmware */ #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL @@ -232,11 +267,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_FSL_MEMAC #define CONFIG_PCI /* Enable PCIE */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */